| Part Number | M2V12D20TP-10L |
| Manufacturer | Mitsubishi |
| Title | 512M Double Data Rate Synchronous DRAM |
| Description | M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit, M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit, double data rate synchronous DRAM, with SSTL_2... |
| Features |
- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge; - data and da... |
| Published | May 2, 2005 |
| Datasheet |
 M2V12D20TP-10L File
|
| Part Number | M2V12D20TP-10 |
| Manufacturer | Mitsubishi |
| Title | 512M Double Data Rate Synchronous DRAM |
| Description | M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit, M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit, double data rate synchronous DRAM, with SSTL_2. |
| Features |
- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge; - data and da. |
| Datasheet |
M2V12D20TP-10 File
|
