| Part Number | M2S56D40ATP-75A |
| Manufacturer | Mitsubishi |
| Title | 256M Double Data Rate Synchronous DRAM |
| Description | M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-bank x 419430... |
| Features |
- VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge - Data and dat... |
| Published | May 2, 2005 |
| Datasheet |
 M2S56D40ATP-75A File
|
| Part Number | M2S56D40ATP-75L |
| Manufacturer | Mitsubishi |
| Title | 256M Double Data Rate Synchronous DRAM |
| Description | M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-bank x 419430. |
| Features |
- VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge - Data and dat. |
| Datasheet |
M2S56D40ATP-75L File
|
| Part Number | M2S56D40ATP-75AL |
| Manufacturer | Mitsubishi |
| Title | 256M Double Data Rate Synchronous DRAM |
| Description | M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-bank x 419430. |
| Features |
- VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge - Data and dat. |
| Datasheet |
M2S56D40ATP-75AL File
|
| Part Number | M2S56D40ATP-75 |
| Manufacturer | Mitsubishi |
| Title | 256M Double Data Rate Synchronous DRAM |
| Description | M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-bank x 419430. |
| Features |
- VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge - Data and dat. |
| Datasheet |
M2S56D40ATP-75 File
|
