| Part Number | M14A |
| Manufacturer | Tyco Electronics |
| Title | DOUBLE-BALANCED MIXER |
| Description | M14A DOUBLE-BALANCED MIXER · LO 4 TO 16 GHz · RF 6 TO 14 GHz · IF DC TO 2 GHz · LO DRIVE +7 dBm (nominal) · HIGH ISOLATION 35 dB (TYP.) · LOW VSWR... |
| Features |
Maximum Ratings
Operating Temperature Storage Temperature Peak Input Power Peak Input Current
Outline Drawing(s)
-54°C to 100°C -65°C to 100°C 23 dBm max. @ +25°, 20°C 100 mA DC
Package SMA Figure CC Model M14A
Specifications subject to change without notice. • North America: 1-800-366-2266 Visit... |
| Published | Mar 30, 2005 |
| Datasheet |
 M14A File
|
| Part Number | M14D5121632A-2.5BG2M |
| Manufacturer | ESMT |
| Title | DDR-II SDRAM |
| Description | ESMT (Preliminary) M14D5121632A (2M) DDR II SDRAM 8M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ±. |
| Features |
JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation. On-chip DLL Differential clock inputs (CLK and CLK ). |
| Datasheet |
M14D5121632A-2.5BG2M File
|
| Part Number | M14D5121632A-2.5BG2A |
| Manufacturer | ESMT |
| Title | DDR-II SDRAM |
| Description | Pin Name A0~A12, BA0,BA1 DQ0~DQ15 RAS CAS WE VSS VDD DQS, DQS (LDQS, LDQS UDQS, UDQS) ODT NC Function Address inputs - Row address A0~A12 - Colu. |
| Features |
JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation. On-chip DLL Differential clock inputs (C. |
| Datasheet |
M14D5121632A-2.5BG2A File
|
| Part Number | M14D5121632A-2.5BBG2M |
| Manufacturer | ESMT |
| Title | DDR-II SDRAM |
| Description | ESMT (Preliminary) M14D5121632A (2M) DDR II SDRAM 8M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ±. |
| Features |
JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation. On-chip DLL Differential clock inputs (CLK and CLK ). |
| Datasheet |
M14D5121632A-2.5BBG2M File
|
| Part Number | M14D5121632A-2.5BBG2A |
| Manufacturer | ESMT |
| Title | DDR-II SDRAM |
| Description | Pin Name A0~A12, BA0,BA1 DQ0~DQ15 RAS CAS WE VSS VDD DQS, DQS (LDQS, LDQS UDQS, UDQS) ODT NC Function Address inputs - Row address A0~A12 - Colu. |
| Features |
JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation. On-chip DLL Differential clock inputs (C. |
| Datasheet |
M14D5121632A-2.5BBG2A File
|
| Part Number | M14D5121632A-1.8BG2M |
| Manufacturer | ESMT |
| Title | DDR-II SDRAM |
| Description | ESMT (Preliminary) M14D5121632A (2M) DDR II SDRAM 8M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ±. |
| Features |
JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation. On-chip DLL Differential clock inputs (CLK and CLK ). |
| Datasheet |
M14D5121632A-1.8BG2M File
|
