| Part Number | M12L64164A-7TG2Y |
| Manufacturer | ESMT |
| Title | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| Description | The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits. Synchronous design allows p... |
| Features |
y JEDEC standard 3.3V power supply y LVTTL compatible with multiplexed address y Four banks operation y MRS cycle with address key programs
- CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) y All inputs are sampled at the positive going edge of the ... |
| Published | Mar 24, 2019 |
| Datasheet |
 M12L64164A-7TG2Y File
|
| Part Number | M12L64164A-7TG2M |
| Manufacturer | ESMT |
| Title | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| Description | The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits. Synchronous design allows pr. |
| Features |
y JEDEC standard 3.3V power supply y LVTTL compatible with multiplexed address y Four banks operation y MRS cycle with address key programs
- CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) y All inputs are sampled at the positive going edge of the . |
| Datasheet |
M12L64164A-7TG2M File
|
| Part Number | M12L64164A-7TG2C |
| Manufacturer | ESMT |
| Title | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| Description | The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits. Synchronous design allows p. |
| Features |
JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clo. |
| Datasheet |
M12L64164A-7TG2C File
|
