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74ALVCH16374 Datasheet PDF

74ALVCH16374
STMicroelectronics

Part Number 74ALVCH16374
Description LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP
Page 11 Pages
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74ALVCH16374
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
s 3.6V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED :
tPD = 4.2 ns (MAX.) at VCC = 3.0 to 3.6V
tPD = 5.3 ns (MAX.) at VCC = 2.3 to 2.7V
tPD = 6.5 ns (MAX.) at VCC = 1.65V
)s POWER DOWN PROTECTION ON INPUTS
t(sAND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
uc|IOH| = IOL = 24mA (MIN) at VCC = 3.0V
d|IOH| = IOL = 18mA (MIN) at VCC = 2.3V
ro )|IOH| = IOL = 4mA (MIN) at VCC = 1.65V
P t(ss OPERATING VOLTAGE RANGE:
VCC(OPR) = 1.65V to 3.6V
te cs PIN AND FUNCTION COMPATIBLE WITH
le du74 SERIES 16374
so ros BUS HOLD PROVIDED ON DATA INPUTS
s LATCH-UP PERFORMANCE EXCEEDS
b P300mA (JESD 17)
- O tes ESD PERFORMANCE:
) leHBM > 2000V (MIL STD 883 method 3015);
t(s oMM > 200V
c bsDESCRIPTION
u OThe 74ALVCH16374 is a low voltage CMOS 16
rod -BIT D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
P t(s)NON INVERTING fabricated with sub-micron
silicon gate and five-layer metal wiring C2MOS
te ctechnology. It is ideal for low power and very high
le uspeed 1.65 to 3.6V applications; it can be
dinterfaced to 3.6V signal environment for both
so roinputs and outputs.
b PThese 16 bit D-TYPE flip-flops are controlled by
two clock inputs (nCK) and two output enable
O teinputs (nOE).
leOn the positive transition of the (nCK), the nQ
ooutputs will be set to the logic state that were
ssetup at the nD inputs.
ObWhile the (nOE) input is low, the outputs (nQ) will
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
PIN CONNECTION
T&R
74ALVCH16374TTR
be in a normal state (HIGH or LOW logic level)
and while high level the outputs will be in a high
impedance state. Any output control does not
affect the internal operation of flip flops; that is, the
old data can be retained or the new data can be
entered even while the outputs are off.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 2003
1/11

















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