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50N03LT Datasheet PDF

50N03LT
NXP Semiconductors

Part Number 50N03LT
Description PHP50N03LT
Page 11 Pages
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Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP50N03LT, PHB50N03LT
PHD50N03LT
FEATURES
’Trench’ technology
• Very low on-state resistance
• Fast switching
www.DataSheetH4Uig.chomthermal cycling performance
• Low thermal resistance
• Logic level compatible
SYMBOL
g
d
s
QUICK REFERENCE DATA
VDSS = 25 V
ID = 48 A
RDS(ON) 16 m(VGS = 10 V)
RDS(ON) 21 m(VGS = 5 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• High frequency computer motherboard d.c. to d.c. converters
• High current switching
The PHP50N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB50N03LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD50N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
SOT78 (TO220AB) SOT404 (D2PAK)
PIN DESCRIPTION
1 gate
tab
tab
SOT428 (DPAK)
tab
2 drain 1
3 source
tab drain
1 23
2
13
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
VGSM
ID
IDM
Ptot
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage (DC)
Gate-source voltage (pulse
peak value)
Drain current (DC)
Drain current (pulse peak
value)
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 k
Tj 150˚C
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
25
25
± 15
± 20
48
34
180
86
175
UNIT
V
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
October 1999
1
Rev 1.800

















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50N03LT datasheet pdf
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NXP Semiconductors
50N03LT pdf



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