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74VHC240 Datasheet PDF

74VHC240
Fairchild Semiconductor

Part Number 74VHC240
Description Octal Buffer/Line Driver with 3-STATE Outputs
Page 7 Pages
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October 1992
Revised March 1999
74VHC240
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The VHC240 is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation. The VHC240 is an inverting 3-STATE buffer having
two active-LOW output enables. This device is designed to
drive buslines or buffer memory address registers.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed: tPD = 3.6ns (typ) at TA = 25°C
s Low power dissipation: ICC = 4 µA (max) @ TA = 25°C
s High noise immunity: VNIH = VNIL = 28% VCC (min)
s Power down protection is provided on all inputs
s Low noise: VOLP = 0.9V (max)
s Pin and function compatible with 74HC240
Ordering Code:
Order Number
74VHC240M
74VHC240SJ
74VHC240MTC
74VHC240N
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
OE1, OE2
I0–I7
O0–O7
Description
3-STATE Output Enable Inputs
Inputs
Outputs 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011506.prf
www.fairchildsemi.com

















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