74VCXH16240 Datasheet PDF

Fairchild Semiconductor

Part Number 74VCXH16240
Description Low Voltage 16-Bit Inverting Buffer/Line Driver with Bushold
Page 7 Pages
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December 1999
Revised March 2000
Low Voltage 16-Bit Inverting Buffer/Line Driver
with Bushold
General Description
The VCXH16240 contains sixteen inverting buffers with 3-
STATE outputs to be employed as a memory and address
driver, clock driver, or bus oriented transmitter/receiver.
The device is nibble (4-bit) controlled. Each nibble has sep-
arate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The VCXH16240 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating inputs at a valid logic level.
The 74VCXH16240 is designed for low voltage (1.65V to
3.6V) VCC applications with output capability up to 3.6V.
The 74VCXH16240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant control inputs and outputs
s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s tPD
2.5 ns max for 3.0V to 3.6V VCC
3.0 ns max for 2.3V to 2.7V VCC
6.0 ns max for 1.65V to 1.95V VCC
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
±18 mA @ 2.3V VCC
±6 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number
Package Descriptions
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Output Enable Input (Active LOW)
Bushold Inputs
© 2000 Fairchild Semiconductor Corporation DS500232

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