August 1986

Revised March 2000

DM74LS390

Dual 4-Bit Decade Counter

General Description

Each of these monolithic circuits contains eight master-

slave flip-flops and additional gating to implement two indi-

vidual four-bit counters in a single package. The

DM74LS390 incorporates dual divide-by-two and divide-

by-five counters, which can be used to implement cycle

lengths equal to any whole and/or cumulative multiples of 2

and/or 5 up to divide-by-100. When connected as a bi-qui-

nary counter, the separate divide-by-two circuit can be

used to provide symmetry (a square wave) at the final out-

put stage. The DM74LS390 has parallel outputs from each

counter stage so that any submultiple of the input count fre-

quency is available for system-timing signals.

Features

s Dual version of the popular DM74LS90

s DM74LS390...individual clocks for A and B flip-flops

provide dual ÷ 2 and ÷ 5 counters

s Direct clear for each 4-bit counter

s Dual 4-bit version can significantly improve system den-

sities by reducing counter package count by 50%

s Typical maximum count frequency...35 MHz

s Buffered outputs reduce possibility of collector commu-

tation

Ordering Code:

Order Number Package Number

Package Description

DM74LS390M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74LS390N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

© 2000 Fairchild Semiconductor Corporation DS006433

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