XR16M570 Datasheet PDF - Exar

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XR16M570
Exar

Part Number XR16M570
Description 1.62V TO 3.63V HIGH PERFORMANCE UART
Page 30 Pages


XR16M570 datasheet pdf
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XR16M570
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
DECEMBER 2009
REV. 1.0.1
GENERAL DESCRIPTION
The XR16M5701 (M570) is an enhanced Universal
Asynchronous Receiver and Transmitter (UART) with
16 bytes of transmit and receive FIFOs, selectable
transmit and receive FIFO trigger levels, automatic
hardware and software flow control, and data rates of
up to 16 Mbps at 3.3V, 12.5 Mbps at 2.5V and 7.5
Mbps at 1.8V with 4X data sampling rate.
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection
increases the performance by simplifying the
software routines.
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. Power consumption of the
M570 can be minimized by enabling the sleep mode
and PowerSave mode.
The M570 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M570 is available in 24-pin
QFN, 32-pin QFN and 25-pin BGA packages. All
three packages offer the 16 mode (Intel bus) interface
only.
NOTE: 1 Covered by U.S. Patent #5,649,122.
FEATURES
Pin-to-pin compatible with XR16L570 in 24-QFN
and 32-QFN packages
Intel data bus Interface
16 Mbps maximum data rate
Selectable TX/RX FIFO Trigger Levels
TX/RX FIFO Level Counters
Independent TX/RX Baud Rate Generator
Fractional Baud Rate Generator
Auto RTS/CTS Hardware Flow Control
Auto XON/XOFF Software Flow Control
Auto RS-485 Half-Duplex Direction Control
Multidrop mode w/ Auto Address Detect
Sleep Mode with Automatic Wake-up
PowerSave mode in 24-pin QFN package
Infrared (IrDA 1.0 and 1.1) mode
1.62V to 3.63V supply operation
Crystal oscillator or external clock input
APPLICATIONS
Personal Digital Assistants (PDA)
Cellular Phones/Data Devices
Battery-Operated Devices
Global Positioning System (GPS)
Bluetooth
FIGURE 1. XR16M570 BLOCK DIAGRAM
PwrSave
A2:A0
D 7 :D 0
IO R #
IOW #
CS#
IN T
RESET
Intel
Data Bus
Interface
UART
UART 16 Byte TX FIFO
Regs TX &
RX
IR
ENDEC
BRG 16 Byte RX FIFO
Crystal Osc/Buffer
VCC
(1.62 to 3.63 V)
GND
TX, RX,
RTS#, CTS#,
DTR#, DSR#,
RI#, CD#
XTAL1
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com



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XR16M570
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
FIGURE 2. PIN OUT ASSIGNMENT FOR 24-PIN QFN, 32-PIN QFN AND 25-BGA PACKAGES
REV. 1.0.1
18 17 16 15 14 13
VCC 19
12
D0 20
11
D1 21
D2 22
24-pin QFN 10
9
D3 23
8
D4 24
7
123456
A2
IOR#
GND
IOW#
CLK
PwrSave
24 23 22 21 20 19 18 17
DSR#
CD#
RI#
VCC
D0
D1
D2
D3
25
26
27
28
29
30
31
32
32-pin QFN
16 NC
15 NC
14 IOR #
13 GND
12 IOW #
11 XTAL 2
10 XTAL 1
9 NC
1 2 3 4 5 67 8
A1 Corner
12 34 5
A
B
C
D
E
CTS#
VCC
D0
D3
D4
Transparent Top View
RESET
DTR#
D6
D1
D2
INT
RTS#
D7
TX
D5
A1
A0
DSR#
CS#
RX
A2
IOR#
IOW#
XTAL1
GND
ORDERING INFORMATION
PART NUMBER
XR16M570IL24
XR16M570IL32
XR16M570IB25
PACKAGE
24-Pin QFN
32-Pin QFN
25-Pin BGA
OPERATING TEMPERATURE
RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
DEVICE STATUS
Active
Active
Active
2



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REV. 1.0.1
PIN DESCRIPTIONS
XR16M570
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
Pin Description
NAME
24-QFN
PIN#
32-QFN
PIN#
25-BGA
PIN#
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2 12
A1 13
A0 14
D7 3
D6 2
D5 1
D4 24
D3 23
D2 22
D1 21
D0 20
IOR#
11
17
18
19
5
4
3
1
32
31
30
29
14
IOW# 9 12
CS# 6 8
INT 15 20
A5 I Address lines [2:0]. These 3 address lines select the internal regis-
A4 ters in UART during a data bus transaction.
B4
C3 I/O Data bus lines [7:0] (bidirectional).
C2
E3
E1
D1
E2
D2
C1
B5 I This input is read strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal reg-
ister pointed by the address lines [A2:A0], puts the data byte on the
data bus to allow the host processor to read it on the rising edge.
C5 I This input is write strobe (active low). The falling edge instigates the
internal write cycle and the rising edge transfers the data byte on
the data bus to an internal register pointed by the address lines.
D4 I This input is chip select (active low) to enable the device.
A3 O This output is the active high device interrupt output. The output
state is defined by the user through the software setting of MCR[3].
INT is set to the active mode when MCR[3] is set to a logic 1. INT is
set to the three state mode when MCR[3] is set to a logic 0. See
MCR[3].
MODEM OR SERIAL I/O INTERFACE
TX 5 7 D3
RX 4 6 E4
RTS# 16 21 B3
CTS# 18 24 A1
DTR# - 22 B2
O UART Transmit Data or infrared encoder data. Standard transmit
and receive interface is enabled when MCR[6] = 0. In this mode,
the TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
I UART Receive Data or infrared receive data. Normal receive data
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
O UART Request-to-Send (active low) or general purpose output.
This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1] and IER[6].
I UART Clear-to-Send (active low) or general purpose input. It can
be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7].
This input should be connected to VCC when not used.
O UART Data-Terminal-Ready (active low) or general purpose output.
3



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XR16M570
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
Pin Description
REV. 1.0.1
NAME
DSR#
CD#
RI#
24-QFN
PIN#
32-QFN
PIN#
25-BGA
PIN#
TYPE
DESCRIPTION
- 25 C4 I UART Data-Set-Ready (active low) or general purpose input. This
input should be connected to VCC when not used.
- 26 - I UART Carrier-Detect (active low) or general purpose input. This
input should be connected to VCC when not used.
- 27 - I UART Ring-Indicator (active low) or general purpose input. This
input should be connected to VCC when not used.
ANCILLARY SIGNALS
XTAL1
8
XTAL2
-
PwrSave
7
10
11
-
D5
-
-
RESET
17
23
A2
VCC
GND
GND
19
10
Center
Pad
28
13
Center
Pad
B1
E5
-
NC - 2, 9, 15, -
16
I Crystal or external clock input.
O Crystal or buffered clock output.
I Power-Save (active high). This feature isolates the M570’s data bus
interface from the host preventing other bus activities that cause
higher power drain during sleep mode. See Sleep Mode with Auto
Wake-up and Power-Save Feature section for details. This pin does
not have a pull-down resistor. This input should be connected to
GND when not used.
I This input is active high. A 40 ns minimum active pulse on this pin
will reset the internal registers and all outputs of the UART. The
UART transmitter output will be held at logic 1, the receiver input
will be ignored and outputs are reset during reset period (see UART
Reset Conditions).
Pwr 1.62V to 3.63V power supply.
Pwr Power supply common, ground.
Pwr The center pad on the backside of the QFN package is metallic and
should be connected to GND on the PCB. The thermal pad size on
the PCB should be the approximate size of this center pad and
should be solder mask defined. The solder mask opening should be
at least 0.0025" inwards from the edge of the PCB thermal pad.
- No Connects.
Pin type: I=Input, O=Output, I/O= Input/output.
4



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