X24320 Datasheet PDF - Xicor


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X24320
Xicor

Part Number X24320
Description 400KHz 2-Wire Serial E2PROM with Block Lock
Page 17 Pages

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32K
X24320
4K x 8 Bit
400KHz 2-Wire Serial E2PROM with Block LockTM
FEATURES
Save Critical Data with Programmable
Block Lock Protection
—Block Lock (0, 1/4, 1/2, or all of E2PROM Array)
—Software Write Protection
—Programmable Hardware Write Protect
In Circuit Programmable ROM Mode
400KHz 2-Wire Serial Interface
—Schmitt Trigger Input Noise Suppression
—Output Slope Control for Ground Bounce
Noise Elimination
Longer Battery Life With Lower Power
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1µA
1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V
Power Supply Versions
32 Word Page Write Mode
—Minimizes Total Write Time Per Word
Internally Organized 4K x 8
Bidirectional Data Transfer Protocol
Self-Timed Write Cycle
—Typical Write Cycle Time of 5ms
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
8-Lead SOIC
14-Lead TSSOP
8-Lead PDIP
FUNCTIONAL DIAGRAM
DESCRIPTION
The X24320 is a CMOS Serial E2PROM, internally
organized 4K x 8. The device features a serial inter-
face and software protocol allowing operation on a
simple two wire bus. The bus operates at 400 KHz all
the way down to 1.8V.
Three device select inputs (S0–S2) allow up to eight
devices to share a common two wire bus.
A Write Protect Register at the highest address loca-
tion, FFFFh, provides three write protection features:
Software Write Protect, Block Lock Protect, and
Programmable Hardware Write Protect. The Software
Write Protect feature prevents any nonvolatile writes to
the device until the WEL bit in the Write Protect
Register is set. The Block Lock Protection feature
gives the user four array block protect options, set by
programming two bits in the Write Protect Register.
The Programmable Hardware Write Protect feature
allows the user to install the device with WP tied to
VCC, write to and Block Lock the desired portions of
the memory array in circuit, and then enable the In
Circuit Programmable ROM Mode by programming the
WPEN bit HIGH in the Write Protect Register. After
this, the Block Locked portions of the array, including
the Write Protect Register itself, are permanently
protected from being erased.
SERIAL E2PROM DATA
AND ADDRESS (SDA)
DATA REGISTER
Y DECODE LOGIC
SCL
S2
S1
S0
COMMAND
DECODE
AND
CONTROL
LOGIC
BLOCK LOCK AND
WRITE PROTECT
CONTROL LOGIC
PAGE
DECODE
LOGIC
DEVICE
SELECT
LOGIC
WRITE
PROTECT
REGISTER
SERIAL E2PROM
ARRAY
4K x 8
1K x 8
1K x 8
2K x 8
WP
©Xicor, 1995, 1996 Patents Pending
7035-1.2 4/25/97 T0/C2/D0 SH
WRITE VOLTAGE
CONTROL
7035 FM 01
Characteristics subject to change without notice
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X24320
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
up resistor selection graph at the end of this data
sheet.
Device Select (S0, S1, S2)
The device select inputs (S0, S1, S2) are used to set
the first three bits of the 8-bit slave address. This
allows up to eight devices to share a common bus.
These inputs can be static or actively driven. If used
statically they must be tied to VSS or VCC as appro-
priate. If actively driven, they must be driven with
CMOS levels (driven to VCC or VSS).
Write Protect (WP)
The Write Protect input controls the Hardware Write
Protect feature. When held LOW, Hardware Write
Protection is disabled. When this input is held HIGH,
and the WPEN bit in the Write Protect Register is set
HIGH, the Write Protect Register is protected,
preventing changes to the Block Lock Protection and
WPEN bits.
PIN NAMES
Symbol
S0, S1, S2
SDA
SCL
WP
VSS
VCC
NC
PIN CONFIGURATION
Description
Device Select Inputs
Serial Data
Serial Clock
Write Protect
Ground
Supply Voltage
No Connect
7035 FM T01
* .197”
S0
S1
S2
VSS
8-Lead DIP/SOIC
18
27
X24320
36
45
Not to scale
VCC
WP
SCL
SDA
* .244”
.200”
S0
S1
NC
NC
NC
S2
VSS
14-Lead TSSOP
1 14
2 13
3 12
4 X24320 11
5 10
69
78
.252”
VCC
WP
NC
NC
NC
SCL
SDA
* SOIC Measurement
7035 FM 02
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X24320
DEVICE OPERATION
The device supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data trans-
fers, and provide the clock for both transmit and
receive operations. Therefore, the device will be
considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE DATA
CHANGE
7035 FM 03
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
7035 FM 04
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X24320
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
The device will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent 8-bit word.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
1
89
ACKNOWLEDGE
7035 FM 05
4




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