X24257 Datasheet PDF - Xicor


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X24257
Xicor

Part Number X24257
Description 400kHz 2-Wire Serial EEPROM
Page 19 Pages

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Preliminary Information
256K
X24257
400kHz 2-Wire Serial EEPROM with Block Lock
32K x 8 Bit
FEATURES
• Save critical data with programmable block lock
protection
—Block lock (first page, first 2 pages, first 4
pages, first 8 pages, 1/4, 1/2, or all of EEPROM
array)
—Software write protection
—Programmable hardware write protect
• In circuit programmable ROM mode
• 400kHz 2-wire serial interface
—Schmitt trigger input noise suppression
—Output slope control for ground bounce noise
elimination
• Longer battery life with lower power
—Active read current less than 1µA
—Active write current less than 3µA
—Standby current less than 1µA
• 2.5V to 5.5V power supply
• 64-byte page write mode
—Minimizes total write time per word
• Internally organized 32K x 8
• Bidirectional data transfer protocol
• Self-timed write cycle
—Typical write cycle time of 5ms
• High reliability
—Endurance: 100,000 cycles
—Data retention: 100 years
• 8-lead XBGA, 8-lead SOIC, 14-lead TSSOP
DESCRIPTION
The X24257 is a CMOS Serial EEPROM, internally
organized 32K x 8. The device features a serial inter-
face and software protocol allowing operation on a
simple two wire bus.
Three device select inputs (S0–S1) allow up to four
devices to share a common two wire bus.
A Write Protect Register at the highest address location,
FFFFh, provides three write protection features: Software
Write Protect, Block Lock Protect, and Programmable
Hardware Write Protect. The Software Write Protect
feature prevents any nonvolatile writes to the device
until the WEL bit in the Write Protect Register is set.
The Block Lock Protection feature gives the user eight
array block protect options, set by programming three
bits in the Write Protect Register. The Programmable
Hardware Write Protect feature allows the user to
install the device with WP tied to VCC, write to and
Block Lock the desired portions of the memory array in
circuit, and then enable the In Circuit Programmable
ROM Mode by programming the WPEN bit HIGH in the
Write Protect Register. After this, the Block Locked
portions of the array, including the Write Protect Register
itself, are protected from being erased if WP is high.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
BLOCK DIAGRAM
Serial EEPROM Data
and Address (SDA)
SCL
S1
S0
Command
Decode
and
Control
Logic
Block Lock and
Write Protect
Control Logic
Device
Select
Logic
Page
Decode
Logic
Write
Protect
Register
WP
Data Register
Y Decode Logic
Serial EEPROM
Array
32K X 8
Write Voltage
Control
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X24257 – Preliminary Information
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
up resistor selection graph at the end of this data
sheet.
Device Select (S0, S1)
The device select inputs (S0, S1) are used to set bits in
the slave address. This allows up to four devices to
share a common bus. These inputs can be static or
actively driven. If used statically they must be tied to
VSS or VCC as appropriate. If actively driven, they must
be driven with CMOS levels (driven to VCC or VSS) and
they must be constant between each start and stop
issued on the SDA bus. These pins have an active pull
down internally and will be sensed as low if the pin is
left unconnected.
Write Protect (WP)
WP must be constant between each start and stop
issued on the SDA bus and is always active (not
gated). The WP pin has an active pull down to disable
the write protection when the input is left floating. The
Write Protect input controls the Hardware Write Protect
feature. When held LOW, Hardware Write Protection is
disabled. When this input is held HIGH, and the WPEN
bit in the Write Protect Register is set HIGH, the Write
Protect Register is protected, preventing changes to
the Block Lock Protection and WPEN bits.
PIN NAMES
Symbol
S0, S1
SDA
SCL
WP
VSS
VCC
NC
PIN CONFIGURATION
Description
Device Select Inputs
Serial Data
Serial Clock
Write Protect
Ground
Supply Voltage
No Connect
8-Lead XBGA: Top View
WP 1
VCC 2
SDA 3
SCL 4
8 S1
7 S0
6 VSS
5 S2
14-Lead TSSOP
S0 1
S1 2
14
13
NC 3
12
NC 4 X24257 11
NC 5
10
S2 6
9
VSS
7
8
VCC
WP
NC
NC
NC
SCL
SDA
8-Lead PDIP/SOIC
S0 1
8 VCC
S1
S2
27
3 X24257 6
WP
SCL
VSS 4
5 SDA
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X24257 – Preliminary Information
DEVICE OPERATION
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the device will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA
Data Stable Data
Change
Figure 2. Definition of Start and Stop
SCL
SDA
Start Bit
Stop Bit
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.
The device will respond with an acknowledge after rec-
ognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent 8-bit word.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
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X24257 – Preliminary Information
Figure 3. Acknowledge Response From Receiver
SCL from
Master
1
Data Output
from Transmitter
89
Data Output
fromReceiver
Start
Acknowledge
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits of
the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 2 bits are the
device select bits S0 and S1. This allows up to 4
devices to share a single bus. These bits are compared
to the S0 and S1 device select input pins. The last bit of
the Slave Address Byte defines the operation to be
performed. When the R/W bit is a one, then a read
operation is selected. When it is zero then a write oper-
ation is selected. Refer to Figure 4. After loading the
Slave Address Byte from the SDA bus, the device com-
pares the device type bits with the value “1010” and the
device select bits with the status of the device select
input pins. If the compare is not successful, no
acknowledge is output during the ninth clock cycle and
the device returns to the standby mode.
On power up the internal address is undefined, so the
first read or write operation must supply an address.
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in Figure 4.
The internal organization of the E2 array is 512 pages
by 64 bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in
bits 7 through 6 of the Word Address Byte 0. The byte
address is contained in bits 5 through 0 of the Word
Address Byte 0. See Figure 4.
Figure 4. Device Addressing
Device Type
Identifier
Device
Select
1 0 1 0 0 S1 S0 R/W
Slave Address Byte
High Order Word Address
* A14 A13 A12 A11 A10 A9 A8
X24257 Word Address Byte 1
*This bit is 0 for access to the array and
1 for access to the Control Register
Low Order Word Address
A7 A6 A5 A4 A3 A2 A1 A0
Word Address Byte 0
D7 D6 D5 D4 D3 D2 D1 D0
Data Byte
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