X24165 Datasheet PDF - Xicor


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X24165
Xicor

Part Number X24165
Description Advanced 2-Wire Serial E2PROM with Block Lock Protection
Page 17 Pages

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Preliminary Information
16K
X24165
2048 x 8 Bit
Advanced 2-Wire Serial E2PROM with Block LockTM Protection
FEATURES
2.7V to 5.5V Power Supply
Low Power CMOS
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1µA
Internally Organized 2048 x 8
New Programmable Block Lock Protection
—Software Write Protection
—Programmable Hardware Write Protect
Block Lock (0, 1/4, 1/2, or all of the E2PROM
array)
2 Wire Serial Interface
Bidirectional Data Transfer Protocol
32 Byte Page Write Mode
—Minimizes Total Write Time Per Byte
Self Timed Write Cycle
—Typical Write Cycle Time of 5ms
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
Available Packages
—8-Lead PDIP
—8-Lead SOIC (JEDEC)
—14-Lead TSSOP
DESCRIPTION
The X24165 is a CMOS 16,384 bit serial E2PROM,
internally organized 2048 x 8. The X24165 features a
serial interface and software protocol allowing opera-
tion on a simple two wire bus.
Three device select inputs (S0, S1, S2) allow up to
eight devices to share a common two wire bus.
A Write Protect Register at the highest address loca-
tion, 7FFh, provides three new write protection
features: Software Write Protect, Block Write Protect,
and Hardware Write Protect. The Software Write
Protect feature prevents any nonvolatile writes to the
X24165 until the WEL bit in the write protect register is
set. The Block Write Protection feature allows the user
to individually write protect four blocks of the array by
programming two bits in the write protect register. The
Programmable Hardware Write Protect feature allows
the user to install the X24165 with WP tied to VCC,
program the entire memory array in place, and then
enable the hardware write protection by programming
a WPEN bit in the write protect register. After this,
selected blocks of the array, including the write protect
register itself, are permanently write protected.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
FUNCTIONAL DIAGRAM
WP
VCC
VSS
SDA
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING &
CONTROL
WRITE PROTECT
REGISTER AND
LOGIC
©Xicor, 1995, 1996 Patents Pending
6551-2.5 5/13/96 T1/C10/D0 NS
SCL
S2
S1
S0
SLAVE ADDRESS
REGISTER
+COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
R/W
DOUT
ACK
1
PIN
XDEC
E2PROM
64 X 256
YDEC
8
CK DATA REGISTER DOUT
6551 ILL F01.1
Characteristics subject to change without notice



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X24165
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
Up Resistor selection graph at the end of this data
sheet.
Device Select (S0, S1, S2)
The device select inputs (S0, S1, S2) are used to set
the first three bits of the 8-bit slave address. This
allows up to eight X24165’s to share a common bus.
These inputs can be static or actively driven. If used
statically they must be tied to VSS or VCC as appro-
priate. If actively driven, they must be driven with
CMOS levels (driven to VCC or VSS).
Write Protect (WP)
The write protect input controls the hardware write
protect feature. When held LOW, hardware write
protection is disabled and the X24165 can be written
normally. When this input is held HIGH, and the WPEN
bit in the write protect register is set HIGH, write
protection is enabled, and nonvolatile writes are
disabled to the selected blocks as well as the write
protect register itself.
PIN NAMES
Symbol
S0, S1, S2
SDA
SCL
WP
VSS
VCC
NC
Description
Device Select Inputs
Serial Data
Serial Clock
Write Protect
Ground
Supply Voltage
No Connect
6551 FRM T01.2
PIN CONFIGURATIONS
8-LEAD DIP & SOIC
S0
S1
S2
VSS
18
27
X24165
36
45
VCC
WP
SCL
SDA
S0
S1
NC
NC
NC
S2
VSS
14-LEAD TSSOP
1 14
2 13
3 12
4 X24165 11
5 10
69
78
VCC
WP
NC
NC
NC
SCL
SDA
6551 ILL F02.5
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X24165
DEVICE OPERATION
The X24165 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the X24165 will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24165 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE DATA
CHANGE
6551 ILL F04
Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V)
(6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
device requires to perform the internal write operation.
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
6551 ILL F05
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X24165
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
The X24165 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the X24165 will respond with an acknowl-
edge after the receipt of each subsequent eight-bit
word.
In the read mode the X24165 will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the X24165
will continue to transmit data. If an acknowledge is not
detected, the X24165 will terminate further data trans-
missions. The master must then issue a stop condition
to return the X24165 to the standby power mode and
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
1
DATA
OUTPUT
FROM
RECEIVER
START
89
ACKNOWLEDGE
6551 ILL F06
4




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