the clock on the ACK bit prior to RTC data output) into
a separate latch to avoid time changes during the read
operation. The clock continues to run.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a seperate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the first “one second” clock cycle after
the stop bit. The RTC continues to update the time
while an RTC register write is in progress and the RTC
continues to run during any nonvolatile write sequences.
A single byte may be written to the RTC without affect-
ing the other bytes.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
logically separated from the array and are only acces-
sible following a slave byte of “1101111x” and reads or
writes to addresses [0000h:003Fh].
The contents of the CCR can be modified by performing
a byte or a page write operation directly to any address in
the CCR. Prior to writing to the CCR (except the status
register), however, the WEL and RWEL bits must be
set using a two step process (See section “Writing to
the Clock/Control Registers.”)
The CCR is divided into 3 sections. These are:
1. Control (2 bytes)
2. Real Time Clock (8 bytes)
3. Status (1 byte)
Sections 1) and 2) are nonvolatile and Section 3) is
volatile. Each register is read and written through buff-
ers. The non-volatile portion (or the counter portion of
the RTC) is updated only if RWEL is set and only after
a valid write operation and stop bit. A sequential read or
page write operation provides access to the contents
of only one section of the CCR per operation. Access
to another section requires a new operation. Contin-
ued reads or writes, once reaching the end of a sec-
tion, will wrap around to the start of the section. A read
or page write can begin at any address in the CCR.
Section 3) is a volatile register. It is not necessary to set
the RWEL bit prior to writing the status register. Section 3)
supports a single byte read or write only. Continued reads
or writes from this section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.