X1227 Datasheet PDF - Intersil Corporation

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X1227
Intersil Corporation

Part Number X1227
Description RTC Real TimeClock/Calendar/ CPU Supervisor
Page 28 Pages


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® NOT RDENaSCtEaEOWESMDhIMSEeELeS1NtIG2D0NE2SD7 FOR
May 8, 2006
X1227
FN8099.2
2-WireRTC Real TimeClock/Calendar/
CPU Supervisor with EEPROM
FEATURES
• Real Time Clock/Calendar
— Tracks Time in Hours, Minutes, and Seconds
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on Chip
— Internal Feedback Resistor and Compensation
Capacitors
— 64 Position Digitally Controlled Trim Capacitor
— 6 Digital Frequency Adjustment Settings to ±30ppm
• CPU Supervisor Functions
— Power-On Reset, Low Voltage Sense
— Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
• Battery Switch or Super Cap Input
• 512 x 8 Bits of EEPROM
— 64-Byte Page Write Mode
— 8 Modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
www.DataSheet4U.com — Data Retention: 100 Years
— Endurance: 100,000 Cycles Per Byte
• 2-Wire™ Interface Interoperable with I2C*
— 400kHz Data Transfer Rate
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
— 8 Ld SOIC and 8 Ld TSSOP
• Repetitive Alarms
• Temperature Compensation
• Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
DESCRIPTION
The X1227 device is a Real Time Clock with
clock/calendar, two polled alarms with integrated 512x8
EEPROM, oscillator compensation, CPU Supervisor
(POR/LVS and WDT) and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
BLOCK DIAGRAM
OSC
Compensation
32.768kHz
X1
X2
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
Battery
Switch
Circuitry
VCC
VBACK
SCL
SDA
Serial
Interface
Decoder
RESET
Control
Decode
Logic
8
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Watchdog
Timer
Low Voltage
Reset
Compare
Alarm Regs
(EEPROM)
4K
EEPROM
ARRAY
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
*I2C is a Trademark of Philips. All other trademarks mentioned are the property of their respective owners.



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X1227
ORDERING INFORMATION
PART NUMBER
X1227S8-4.5A
PART MARKING VCC RANGE (V)
VTRIP
TEMPERATURE
RANGE (°C)
PACKAGE
X1227AL
4.5 to 5.5
4.63V ± 112mV
0 to 70
8 Ld SOIC
PKG. DWG. #
MDP0027
X1227S8Z-4.5A (Note 1) X1227ZAL
0 to 70
8 Ld SOIC (Pb-free) MDP0027
X1227S8I-4.5A
X1227AM
-40 to 85 8 Ld SOIC
MDP0027
X1227S8IZ-4.5A (Note 1) X1227ZAM
-40 to 85 8 Ld SOIC (Pb-free) MDP0027
X1227V8-4.5A
1227AL
0 to 70
8 Ld TSSOP
M8.173
X1227V8Z-4.5A (Note 1) 1227ALZ
0 to 70
8 Ld TSSOP (Pb-free) M8.173
X1227V8I-4.5A
1227AM
-40 to 85 8 Ld TSSOP
M8.173
X1227V8IZ-4.5A (Note 1) 1227AMZ
-40 to 85 8 Ld TSSOP (Pb-free) M8.173
X1227S8*
X1227
4.38V ± 112mV
0 to 70
8 Ld SOIC
MDP0027
X1227S8Z* (Note 1)
X1227Z
0 to 70
8 Ld SOIC (Pb-free) MDP0027
X1227S8I
X1227I
-40 to 85 8 Ld SOIC
MDP0027
X1227S8IZ (Note 1)
X1227ZI
-40 to 85 8 Ld SOIC (Pb-free) MDP0027
X1227V8
1227
0 to 70
8 Ld TSSOP
M8.173
X1227V8Z (Note 1)
1227Z
0 to 70
8 Ld TSSOP (Pb-free) M8.173
X1227V8I
1227I
-40 to 85 8 Ld TSSOP
M8.173
X1227V8IZ (Note 1)
1227IZ
-40 to 85 8 Ld TSSOP (Pb-free) M8.173
X1227S8-2.7A
X1227S8Z-2.7A (Note 1)
X1227AN
X1227ZAN
2.7 to 5.5
2.85V ± 100mV
0 to 70
0 to 70
8 Ld SOIC
8 Ld SOIC (Pb-free)
MDP0027
MDP0027
X1227S8I-2.7A*
X1227AP
-40 to 85 8 Ld SOIC
MDP0027
X1227S8IZ-2.7A* (Note 1) X1227ZAP
-40 to 85 8 Ld SOIC (Pb-free) MDP0027
X1227V8-2.7A
1227AN
0 to 70
8 Ld TSSOP
M8.173
X1227V8Z-2.7A (Note 1) 1227ANZ
0 to 70
8 Ld TSSOP (Pb-free) M8.173
X1227V8I-2.7A
1227AP
-40 to 85 8 Ld TSSOP
M8.173
X1227V8IZ-2.7A (Note 1) 1227APZ
-40 to 85 8 Ld TSSOP (Pb-free) M8.173
X1227S8-2.7*
X1227F
2.65V ± 100mV
0 to 70
8 Ld SOIC
MDP0027
X1227S8Z-2.7 (Note 1)
X1227ZF
0 to 70
8 Ld SOIC (Pb-free) MDP0027
X1227S8I-2.7*
X1227G
-40 to 85 8 Ld SOIC
MDP0027
X1227S8IZ-2.7 (Note 1) X1227ZG
-40 to 85 8 Ld SOIC (Pb-free) MDP0027
X1227V8-2.7
1227F
0 to 70
8 Ld TSSOP
M8.173
X1227V8Z-2.7 (Note 1)
1227FZ
0 to 70
8 Ld TSSOP (Pb-free) M8.173
X1227V8I-2.7
1227G
-40 to 85 8 Ld TSSOP
M8.173
X1227V8IZ-2.7 (Note 1) 1227GZ
-40 to 85 8 Ld TSSOP (Pb-free) M8.173
*Add "T1" suffix for tape and reel.
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For appropriate volume, any VTRIP value from 2.6 to 4.7V may be ordered via Intersil’s Customer Specification Program (CSPEC).
2 FN8099.2
May 8, 2006



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PIN DESCRIPTIONS
X1227
X1
X2
RESET
VSS
X1227
8 LD SOIC
18
27
36
45
VCC
VBACK
SCL
SDA
NC = No internal connection
VBACK
VCC
X1
X2
X1227
8 LD TSSOP
18
27
36
45
SCL
SDA
VSS
RESET
PIN ASSIGNMENTS
Pin Number
SOIC
TSSOP
13
24
35
46
57
68
71
82
Symbol
X1
X2
RESET
VSS
SDA
SCL
VBACK
VCC
Brief Description
X1. The X1 pin is the input of an inverting amplifier and should be connected to one
pin of a 32.768kHz quartz crystal.
X2. The X2 pin is the output of an inverting amplifier and should be connected to
one pin of a 32.768kHz quartz crystal..
Reset Output – RESET. This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or that the voltage has
dropped below a fixed VTRIP threshold. It is an open drain active LOW output.
VSS.
Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of
the device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs.
Serial Clock (SCL). The SCL input is used to clock all data into and out of the
device. The input buffer on this pin is always active (not gated).
VBACK. This input provides a backup supply voltage to the device. VBACK supplies
power to the device in the event the VCC supply fails. This pin can be connected to
a battery, a Supercap or tied to ground if not used.
VCC.
3 FN8099.2
May 8, 2006



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X1227
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................... -65°C to +135°C
Storage Temperature ........................ -65°C to +150°C
Voltage on VCC, VBACK pin
(respect to ground)...............................-0.5V to 7.0V
Voltage on SCL, SDA, X1 and X2
pin (respect to ground) ............... -0.5V to 7.0V or 0.5V
above VCC or VBACK (whichever is higher)
DC Output Current .............................................. 5 mA
Lead Temperature (Soldering, 10 sec) .............. 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may
affect device reliability.
DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.)
Symbol
VCC
VBACK
VCB
VBC
Parameter
Main Power Supply
Backup Power Supply
Switch to Backup Supply
Switch to Main Supply
Conditions
Min
Typ
Max
Unit
2.7 5.5 V
1.8 5.5 V
VBACK -0.2
VBACK
VBACK -0.1
VBACK +0.2
V
V
Notes
OPERATING CHARACTERISTICS
Symbol
ICC1
Parameter
Read Active Supply
Current
ICC2 Program Supply Current
(nonvolatile)
ICC3
Main Timekeeping
Current
IBACK
ILI
ILO
VIL
Timekeeping Current –
(Low Voltage Sense
and Watchdog Timer
disabled
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Conditions
VCC = 2.7V
VCC = 5.0V
VCC = 2.7V
VCC = 5.0V
VCC = 2.7V
VCC = 5.0V
VBACK = 1.8V
VBACK = 3.3V
Min
-0.5
VIH
VHYS
VOL1
Input HIGH Voltage
Schmitt Trigger Input
Hysteresis
Output LOW Voltage for
SDA and RESET
VCC related level
VCC = 2.7V
VCC = 5.5V
VCC x 0.7 or
VBACK x 0.7
.05 x VCC or
.05 x VBACK
Typ
1.25
1.5
Max
400
800
2.5
3.0
10
20
Unit
µA
µA
mA
mA
µA
µA
µA
µA
Notes
1, 5, 7, 14
2, 5, 7, 14
3, 7, 8, 14, 15
3, 6, 9, 14, 15
“See Perfor-
mance Data”
10
10
VVCBCACxK0x.20.o2r
VCC + 0.5 or
VBACK + 0.5
µA
µA
V
V
V
10
10
13
13
13
0.4 V
0.4
11
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address
Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(4) For reference only and not tested.
(5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz
(6) VCC = 0V
(7) VBACK = 0V
(8) VSDA = VSCL=VCC, Others = GND or VCC
4 FN8099.2
May 8, 2006



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