X1226 Datasheet PDF - Xicor

www.Datasheet-PDF.com

X1226
Xicor

Part Number X1226
Description Real Time Clock/Calendar with EEPROM
Page 24 Pages


X1226 datasheet pdf
Download PDF
X1226 pdf
View PDF for Mobile


No Preview Available !

4K (512 x 8)
New Features
Repetitive Alarms &
Temperature Compensation
X1226
Real Time Clock/Calendar with EEPROM
2-WireRTC
FEATURES
• Real Time Clock/Calendar
—Tracks time in Hours, Minutes, and Seconds
—Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
—Settable on the Second, Minute, Hour, Day of
the Week, Day, or Month
—Repeat Mode (periodic interrupts)
• Oscillator Compensation on chip
—Internal feedback resistor and compensation
capacitors
—64 position Digitally Controlled Trim Capacitor
—6 digital frequency adjustment settings to
±30ppm
• Battery Switch or Super Cap Input
• 512 x 8 Bits of EEPROM
—64-Byte Page Write Mode
—8 modes of Block Lock™ Protection
—Single Byte Write Capability
• High Reliability
—Data Retention: 100 years
—Endurance: 100,000 cycles per byte
• 2-Wire™ Interface interoperable with I2C*
—400kHz data transfer rate
• Frequency Output (SW Selectable: Off, 1Hz,
4096Hz or 32.768kHz)
• Low Power CMOS
—1.25µA Operating Current (Typical)
• Small Package Options
—8-Lead SOIC and 8-Lead TSSOP
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio / Video Components
• Set Top Box / Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers / PDA
• POS Equipment
• Test Meters / Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial / Medical / Automotive
DESCRIPTION
The X1226 device is a Real Time Clock with clock/
calendar, two polled alarms with integrated 512x8
EEPROM, oscillator compensation, and battery
backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
BLOCK DIAGRAM
32.768kHz
X1
X2
PHZ/IRQ
Select
SCL
SDA
Serial
Interface
Decoder
Control
Decode
Logic
8
*I2C is a Trademark of Philips.
REV 1.1.24 1/13/03
OSC
Compensation
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Compare
Alarm Regs
(EEPROM)
4K
EEPROM
ARRAY
Battery
Switch
Circuitry
VCC
VBACK
www.xicor.com
Characteristics subject to change without notice. 1 of 24



No Preview Available !

X1226
DESCRIPTION (continued)
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, Seconds. The Calendar
has separate registers for Date, Month, Year and Day-
of-week. The calendar is correct through 2099, with
automatic leap year correction.
The powerful Dual Alarms can be set to any Clock/
Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide
a hardware interrupt (IRQ Pin). There is a repeat
mode for the alarms allowing a periodic interrupt.
The PHZ/IRQ pin may be software selected to provide
a frequency output of 1 Hz, 4096 Hz, or 32,768 Hz.
The device offers a backup power input pin. This
VBACK pin allows the device to be backed up by battery
or SuperCap. The entire X1226 device is fully
operational from 2.7 to 5.5 volts and the clock/calendar
portion of the X1226 device remains fully operational
down to 1.8 volts (Standby Mode).
The X1226 device provides 4K bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock allows a
safe, secure memory for critical user and configuration
data, while allowing a large user storage area.
PIN DESCRIPTIONS
X1226
X1
X2
PHZ/IRQ
VSS
8-Pin SOIC
18
27
36
45
VCC VBACK
VBACK VCC
SCL X1
SDA
X2
8-Pin TSSOP
18
27
36
45
SCL
SDA
VSS
PHZ/IRQ
NC = No internal connection
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire inter-
face speed.
VBACK
This input provides a backup supply voltage to the
device. VBACK supplies power to the device in the
event the VCC supply fails. This pin can be connected
to a battery, a Supercap or tied to ground if not used.
Programmable Frequency/Interrupt Output – PHZ/IRQ
This is either an output from the internal oscillator or an
interrupt signal output. It is an open drain output.
When used as frequency output, this signal has a
frequency of 32.768kHz, 4096Hz, 1Hz or inactive.
When used as interrupt output, this signal notifies a
host processor that an alarm has occurred and an
action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and
are found in address 0011h of the Clock Control Mem-
ory map. Refer to “Programmable Frequency Output
Bits” on page 6.
X1, X2
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external
32.768kHz quartz crystal is used with the X1226 to
supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit.
Plenty of ground plane around the device and short
traces to X1 and X2 are highly recommended. See
Application section for more recommendations.
Figure 1. Recommended Crystal connection
X1
X2
POWER CONTROL OPERATION
The power control circuit accepts a VCC and a VBACK
input. The power control circuit powers the clock from
VBACK when VCC < VBACK – 0.2V. It will switch back to
power the device from VCC when VCC exceeds VBACK.
REV 1.1.24 1/13/03
www.xicor.com
Characteristics subject to change without notice. 2 of 24



No Preview Available !

X1226
Figure 2. Power Control
VCC
VBACK
Off
Voltage
On
In
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external
32.768kHz quartz crystal to maintain an accurate
internal representation of the second, minute, hour,
day, date, month, and year. The RTC has leap-year
correction. The clock also corrects for months having
fewer than 31 days and has a bit that controls 24 hour
or AM/PM format. When the X1226 powers up after
the loss of both VCC and VBACK, the clock will not
operate until at least one byte is written to the clock
register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change during
the course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a separate
latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a
read are unaffected by the read operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the next “one second” clock cycle after
the stop bit is written. The RTC continues to update
the time while an RTC register write is in progress and
the RTC continues to run during any nonvolatile write
sequences. A single byte may be written to the RTC
without affecting the other bytes.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC perfor-
mance will also be dependent upon temperature. The
frequency deviation of the crystal is a fuction of the
turnover temperature of the crystal from the crystal’s
nominal frequency. For example, a >20ppm frequency
deviation translates into an accuracy of >1 minute per
month. These parameters are available from the
crystal manufacturer. Xicor’s RTC family provides on-
chip crystal compensation networks to adjust load-
capacitance to tune oscillator frequency from +116
ppm to –37 ppm when using a 12.5 pF load crystal.
For more detail information see the Application
section.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
CCR Access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
REV 1.1.24 1/13/03
www.xicor.com
Characteristics subject to change without notice. 3 of 24



No Preview Available !

X1226
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 (status register) supports
a single byte read or write only. Continued reads or
writes from this section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Addi-
tional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
change the time being read. A sequential read of the
CCR will not result in the output of data from the mem-
ory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
Table 1. Clock/Control Memory Map
Addr.
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
000F
000E
000D
000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
Type
Status
RTC
(SRAM)
Control
(EEPROM)
Alarm1
(EEPROM)
Alarm0
(EEPROM)
Reg
Name
SR
Y2K
DW
YR
MO
DT
HR
MN
SC
DTR
ATR
INT
BL
Y2K1
DWA1
YRA1
MOA1
DTA1
HRA1
MNA1
SCA1
Y2K0
DWA0
YRA0
MOA0
DTA0
HRA0
MNA0
SCA0
7
BAT
0
0
Y23
0
0
MIL
0
0
0
0
IM
BP2
0
EDW1
EMO1
EDT1
EHR1
EMN1
ESC1
0
EDW0
EMO0
EDT0
EHR0
EMN0
ESC0
Bit
65 4 3 2 1
AL1 AL0
0
0
RWEL
WEL
0 Y2K21 Y2K20 Y2K13
0
0
0 0 0 0 DY2 DY1
Y22 Y21 Y20 Y13 Y12 Y11
0 0 G20 G13 G12 G11
0 D21 D20 D13 D12 D11
0 H21 H20 H13 H12 H11
M22 M21 M20 M13 M12 M11
S22 S21 S20 S13 S12 S11
0 0 0 0 DTR2 DTR1
0 ATR5 ATR4 ATR3 ATR2 ATR1
AL1E AL0E
FO1
FO0
X
X
BP1 BP0
0
0
0
0
0 A1Y2K21 A1Y2K20 A1Y2K13
0
0
0 0 0 0 DY2 DY1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0 0 A1G20 A1G13 A1G12 A1G11
0 A1D21 A1D20 A1D13 A1D12 A1D11
0 A1H21 A1H20 A1H13 A1H12 A1H11
A1M22 A1M21 A1M20 A1M13 A1M12 A1M11
A1S22 A1S21 A1S20 A1S13 A1S12 A1S11
0 A0Y2K21 A0Y2K20 A0Y2K13
0
0
0 0 0 0 DY2 DY1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0 0 A0G20 A0G13 A0G12 A0G11
0 A0D21 A0D20 A0D13 A0D12 A0D11
0 A0H21 A0H20 A0H13 A0H12 A0H11
A0M22 A0M21 A0M20 A0M13 A0M12 A0M11
A0S22 A0S21 A0S20 A0S13 A0S12 A0S11
0 (optional)
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
DTR0
ATR0
X
0
A1Y2K10
DY0
Range
19/20
0-6
0-99
1-12
1-31
0-23
0-59
0-59
19/20
0-6
A1G10
A1D10
A1H10
A1M10
A1S10
A0Y2K10
DY0
1-12
1-31
0-23
0-59
0-59
19/20
0-6
A0G10
A0D10
A0H10
A0M10
A0S10
1-12
1-31
0-23
0-59
0-59
01h
20h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h
REV 1.1.24 1/13/03
www.xicor.com
Characteristics subject to change without notice. 4 of 24



X1226 datasheet pdf
Download PDF
X1226 pdf
View PDF for Mobile


Related : Start with X122 Part Numbers by
X1226 Real Time Clock/Calendar with EEPROM X1226
Xicor
X1226 pdf
X1226 Real Time Clock/Calendar X1226
Intersil Corporation
X1226 pdf
X1227 Real Time Clock/Calendar/CPU Supervisor with EEPROM X1227
Xicor
X1227 pdf
X1227 RTC Real TimeClock/Calendar/ CPU Supervisor X1227
Intersil Corporation
X1227 pdf
X1228 Real Time Clock/Calendar/CPU Supervisor with EEPROM X1228
Xicor
X1228 pdf
X1228 Real Time Clock/Calendar/CPU Supervisor X1228
Intersil Corporation
X1228 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact