X1205 Datasheet PDF - Xicor

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X1205
Xicor

Part Number X1205
Description Real Time Clock/Calendar
Page 22 Pages


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Preliminary Information
New Features
Repetitive Alarms &
Temperature Compensation
X1205
Real Time Clock/Calendar
2-WireRTC
FEATURES
• Real Time Clock/Calendar
—Tracks time in Hours, Minutes, and Seconds
—Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
—Settable on the Second, Minute, Hour, Day of
the Week, Day, or Month
—Repeat Mode (periodic interrupts)
• Oscillator Compensation on chip
—Internal feedback resistor and compensation
capacitors
—64 position Digitally Controlled Trim Capacitor
—6 digital frequency adjustment settings to
±30ppm
• Battery Switch or Super Cap Input
• 2-Wire™ Interface interoperable with I2C*
—400kHz data transfer rate
• Low Power CMOS
—1.25µA Operating Current (Typical)
• Small Package Options
—8-Lead SOIC and 8-Lead TSSOP
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio / Video Components
• Set Top Box / Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers / PDA
• POS Equipment
• Test Meters / Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial / Medical / Automotive
DESCRIPTION
The X1205 device is a Real Time Clock with clock/
calendar, two polled alarms, oscillator compensation,
and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, and Seconds. The
Calendar has separate registers for Date, Month, Year
and Day-of-week. The calendar is correct through
2099, with automatic leap year correction.
BLOCK DIAGRAM
OSC
Compensation
32.768kHz
X1
X2
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
SCL
SDA
Serial
Interface
Decoder
IRQ
Control
Decode
Logic
8
*I2C is a Trademark of Philips.
REV 1.0.9 8/29/02
Control
Registers
(EEPROM)
Status
Registers
(SRAM)
Interrupt Enable
Alarm
www.xicor.com
Alarm
Compare
Alarm Regs
(EEPROM)
Characteristics subject to change without notice. 1 of 22



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X1205 – Preliminary Information
DESCRIPTION (continued)
The powerful Dual Alarms can be set to any Clock/
Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide
a hardware interrupt (IRQ Pin). There is a repeat
mode for the alarms allowing a periodic interrupt.
The device offers a backup power input pin. This
VBACK pin allows the device to be backed up by battery
or SuperCap. The entire X1205 device is fully
operational from 2.7 to 5.5 volts and the clock/calendar
portion of the X1205 device remains fully operational
down to 1.8 volts (Standby Mode).
PIN DESCRIPTIONS
X1205
X1, X2
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external
32.768kHz quartz crystal is used with the X1205 to
supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit.
Plenty of ground plane around the device and short
traces to X1 and X2 are highly recommended. See
Application section for more recommendations.
Figure 1. Recommended Crystal connection
X1
X2
X1
X2
IRQ
VSS
8-Pin SOIC
18
27
36
45
VCC VBACK
VBACK VCC
SCL X1
SDA
X2
8-Pin TSSOP
18
27
36
45
SCL
SDA
VSS
IRQ
NC = No internal connection
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire inter-
face speeds.
VBACK
This input provides a backup supply voltage to the
device. VBACK supplies power to the device in the
event the VCC supply fails. This pin can be connected
to a battery, a Supercap or tied to ground if not used.
Interrupt Output – IRQ
This is an interrupt signal output. This signal notifies a
host processor that an alarm has occurred and
requests action. It is an open drain active low output.
POWER CONTROL OPERATION
The power control circuit accepts a VCC and a VBACK
input. The power control circuit powers the clock from
VBACK when VCC < VBACK - 0.2V. It will switch back to
power the device from VCC when VCC exceeds VBACK.
Figure 2. Power Control
VBACK
VCC
Off
Voltage
On
In
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external
32.768kHz quartz crystal to maintain an accurate inter-
nal representation of second, minute, hour, day, date,
month, and year. The RTC has leap-year correction.
The clock also corrects for months having fewer than
31 days and has a bit that controls 24 hour or AM/PM
format. When the X1205 powers up after the loss of
both VCC and VBACK, the clock will not operate until at
least one byte is written to the clock register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change during
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Characteristics subject to change without notice. 2 of 22



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X1205 – Preliminary Information
the course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a separate
latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a
read are unaffected by the read operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the next “one second clock cycle” after
the stop bit is written. The RTC continues to update
the time while an RTC register write is in progress and
the RTC continues to run during any nonvolatile write
sequences. A single byte may be written to the RTC
without affecting the other bytes.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC perfor-
mance will also be dependent upon temperature. The
frequency deviation of the crystal is a function of the
turnover temperature of the crystal from the crystal’s
nominal frequency. For example, a >20ppm frequency
deviation translates into an accuracy of >1 minute per
month. These parameters are available from the
crystal manufacturer. Xicor’s RTC family provides on-
chip crystal compensation networks to adjust load-
capacitance to tune oscillator frequency from +116
ppm to –37 ppm when using a 12.5 pF load crystal.
For more detail information see the Application
section.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
CCR access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Addi-
tional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
change the time being read. A sequential read of the
CCR will not result in the output of data from the mem-
ory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
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X1205 – Preliminary Information
– Setting the Enable Month Bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
*n = 0 for Alarm 0: N = 1 for Alarm 1
When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
– The user can set the X1205 to alarm every Wednes-
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00AM
Wednesday.
– A daily alarm for 9:30PM results when the EHRn*
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30PM.
*n = 0 for Alarm 0: N = 1 for Alarm 1
Table 1. Clock/Control Memory Map
Addr.
Type
Reg
Name
7
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
Status
RTC (SRAM)
Control
(NONVOLATILE)
SR
Y2K
DW
YR
MO
DT
HR
MN
SC
DTR
ATR
INT
0
BAT
0
0
Y23
0
0
MIL
0
0
0
0
IM
0
000F Alarm1 Y2K1
000E (NONVOLATILE) DWA1
000D
YRA1
000C
MOA1
000B
DTA1
000A
HRA1
0009
MNA1
0008
SCA1
0007 Alarm0 Y2K0
0006 (NONVOLATILE) DWA0
0005
YRA0
0004
MOA0
0003
DTA0
0002
HRA0
0001
MNA0
0000
SCA0
0
EDW1
EMO1
EDT1
EHR1
EMN1
ESC1
0
EDW0
EMO0
EDT0
EHR0
EMN0
ESC0
Bit
65 4 3 2 1
AL1
0
0
Y22
0
0
0
M22
S22
0
0
AL1E
0
AL0
Y2K21
0
Y21
0
D21
H21
M21
S21
0
ATR5
AL0E
0
0
Y2K20
0
Y20
G20
D20
H20
M20
S20
0
ATR4
0
0
0
Y2K13
0
Y13
G13
D13
H13
M13
S13
0
ATR3
0
0
RWEL
0
DY2
Y12
G12
D12
H12
M12
S12
DTR2
ATR2
X
0
WEL
0
DY1
Y11
G11
D11
H11
M11
S11
DTR1
ATR1
X
0
0 A1Y2K21 A1Y2K20 A1Y2K13 0
0
0 0 0 0 DY2 DY1
Unused – Default = RTC Year value – Future expansion
0 0 A1G20 A1G13 A1G12 A1G11
0 A1D21 A1D20 A1D13 A1D12 A1D11
0 A1H21 A1H20 A1H13 A1H12 A1H11
A1M22 A1M21 A1M20 A1M13 A1M12 A1M11
A1S22 A1S21 A1S20 A1S13 A1S12 A1S11
0 A0Y2K21 A0Y2K20 A0Y2K13 0
0
0 0 0 0 DY2 DY1
Unused – Default = RTC Year value – Future expansion
0 0 A0G20 A0G13 A0G12 A0G11
0 A0D21 A0D20 A0D13 A0D12 A0D11
0 A0H21 A0H20 A0H13 A0H12 A0H11
A0M22 A0M21 A0M20 A0M13 A0M12 A0M11
A0S22 A0S21 A0S20 A0S13 A0S12 A0S11
Range
0
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
DTR0
ATR0
X
0
0-6
0-99
1-12
1-31
0-23
0-59
0-59
A1Y2K10
DY0 0-6
A1G10
A1D10
A1H10
A1M10
A1S10
A0Y2K10
DY0
1-12
1-31
0-23
0-59
0-59
19/20
0-6
A0G10
A0D10
A0H10
A0M10
A0S10
1-12
1-31
0-23
0-59
0-59
01h
20h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h
REV 1.0.9 8/29/02
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Characteristics subject to change without notice. 4 of 22



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