V58C2256404SC Datasheet PDF - ProMOS Technologies

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V58C2256404SC
ProMOS Technologies

Part Number V58C2256404SC
Description 256 Mbit DDR SDRAM
Page 30 Pages


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V58C2256(804/404/164)SC*I
256 Mbit DDR SDRAM, INDUSTRIAL TEMPERATURE
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4 BANKS X 16Mbit X 4 (404)
Clock Cycle Time (tCK2)
Clock Cycle Time (tCK2.5)
Clock Cycle Time (tCK3)
System Frequency (fCK max)
5B
DDR400
7.5 ns
5ns
5ns
200 MHz
5
DDR400
7.5 ns
6ns
5ns
200 MHz
6
DDR333
7.5 ns
6 ns
6 ns
166 MHz
7
DDR266
7.5ns
7ns
7 ns
143 MHz
Features
High speed data transfer rates with system frequency
up to 200 MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 2.5, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 66-pin 400 mil TSOP or 60 Ball FBGA
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
Differential clock inputs CK and CK
Power Supply 2.5V ± 0.2V
Power Supply 2.6V ± 0.1V for DDR400
tRAS lockout supported
Concurrent auto precharge option is supported
Industrial Temperature (TA): -40C to +85C
*Note: (-5B) Supports PC3200 module with 2.5-3-3 timing
(-5) Supports PC3200 module with 3-3-3 timing
(-6) Supports PC2700 module with 2.5-3-3 timing
(-7) Supports PC2100 module with 2-2-2 timing
Description
The V58C2256(804/404/164)SC*I is a four bank DDR
DRAM organized as 4 banks x 8Mbit x 8 (804), 4 banks x
4Mbit x 16 (164), or 4 banks x 16Mbit x 4 (404). The
V58C2256(804/404/164)SC*I achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
JEDEC 66 TSOP II
60 FBGA
-40°C to +85°C
V58C2256(804/404/164)SC*I Rev.1.4 March 2007
CK Cycle Time (ns)
-5B -5
-6
•••
1
-7
Power
Std.
L
Temperature
Mark
I
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ProMOS TECHNOLOGIES
V58C2256(804/404/164)SC*I
Part Number Information
1 23 4 5
6 7 8 9 10
V 58 C 2
25680
ProMOS
ORGANIZATION
& REFRESH
32Mx4, 4K : 12840 8Mx16, 4K : 12816
16Mx8, 4K : 12880
64Mx4, 8K : 25640 16Mx16, 8K : 25616
32Mx8, 8K : 25680 8Mx32, 4K : 25632
TYPE
128Mx4, 8K : 51240 32Mx16, 8K : 51216
58 : DDR
56 : MOBILE DDR
64Mx8, 8K : 51280
256Mx4, 8K : G0140 64Mx16, 8K : G0116
128Mx8, 8K : G0180
11 12 13 14
4 SC
CMOS
VOLTAGE
2 : 2.5 V
1 : 1.8 V
BANKS
2 : 2 BANKS
4 : 4 BANKS
8 : 8 BANKS
I/O
S: SSTL_2
REV LEVEL
A: 1st C: 3rd
B: 2nd D: 4th
SPECIAL FEATURE
L : LOW POWER GRADE
U : ULTRA LOW POWER GRADE
15 16 17 18
T5
19
I
TEMPERATURE
BLANK: 0 - 70C
I : -40 - 85C
E : -40 - 125C
SPEED
8 : 125MHz @CL3-3-3
5D : 200MHz @CL2-3-3
75 : 133MHz @CL2.5-3-3
7 : 133MHz @CL2-2-2
4 : 250MHz @CL4-4-4
37 : 266MHz @CL4-4-4
6 : 166MHz @CL2.5-3-3
5 : 200MHz @CL3-3-3
36 : 275MHz @CL4-4-4
33 : 300MHz @CL4-4-4
5B : 200MHz @CL2.5-3-3 3 : 333MHz @CL5-5-5
PACKAGE
28 : 350MHz @CL5-5-5
LEAD
RoHS GREEN PACKAGE
PLATING
DESCRIPTION
T
EI
TSOP
S F J FBGA
B H M BGA
D N Die-stacked TSOP
Z R P Die-stacked FBGA
*RoHS: Restriction of Hazardous Substances
*GREEN: RoHS-compliant and Halogen-Free
V58C2256(804/404/164)SC*I Rev. 1.4 March 2007
2
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ProMOS TECHNOLOGIES
V58C2256(804/404/164)SC*I
60-Ball FBGA PIN OUT
(x4) 1
23
78
9 (x8) 1
23
78
9
VSSQ NC VSS A VDD NC VDDQ
NC VDDQ DQ3 B DQ0 VSSQ NC
NC VSSQ NC C
NC VDDQ NC
NC VDDQ DQ2 D DQ1 VSSQ NC
NC VSSQ DQS
VREF VSS DM
E
F
NC VDDQ NC
NC VDD NC
CK CK G
A12 CKE H
WE
RAS
CAS
CS
A11 A9 J BA1 BA0
A8 A7 K A0 A10/AP
A6 A5 L A2 A1
A4 VSS M VDD A3
X4 Device Ball Pattern
VSSQ DQ7 VSS A VDD DQ0 VDDQ
NC VDDQ DQ6 B DQ1 VSSQ NC
NC VSSQ DQ5 C DQ2 VDDQ NC
NC VDDQ DQ4 D DQ3 VSSQ NC
NC VSSQ DQS
VREF VSS DM
E
F
NC VDDQ NC
NC VDD NC
CK CK G
A12 CKE H
WE
RAS
CAS
CS
A11 A9 J BA1 BA0
A8 A7 K A0 A10/AP
A6 A5 L A2 A1
A4 VSS M VDD A3
X8 Device Ball Pattern
(x16) 1
23
78
9
VSSQ DQ15 VSS A VDD DQ0 VDDQ
DQ14 VDDQ DQ13 B DQ2 VSSQ DQ1
DQ12 VSSQ DQ11 C DQ4 VDDQ DQ3
DQ10 VDDQ DQ9 D DQ6 VSSQ DQ5
DQ8 VSSQ UDQS
VREF VSS UDM
E
F
LDQS VDDQ DQ7
LDM VDD NC
CK CK G WE CAS
A12 CKE H RAS CS
A11 A9 J BA1 BA0
A8 A7 K A0 A10/AP
A6 A5 L A2 A1
A4 VSS M VDD A3
X16 Device Ball Pattern
PIN A1 INDEX
123
A
B
789
C
D
E
F
G
H
J
K
L
M
TOP VIEW
(See the ball through the package)
V58C2256(804/404/164)SC*I Rev. 1.4 March 2007
3
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ProMOS TECHNOLOGIES
V58C2256(804/404/164)SC*I
66 Pin Plastic TSOP-II
PIN CONFIGURATION
Top16VMibexw16
32Mb x 8
64Mb x 4
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
LDQS
VDDQ
NC
NC NC
VDD
VDD
NC NC
LDM NC
WE
CAS
WE
CAS
RAS RAS
CS CS
NC NC
BA0
BA1
BA0
BA1
AP/A10 AP/A10
A0
A1
A2
A3
VDD
A0
A1
A2
A3
VDD
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
66 PIN
(400mil
TSOP
x 875
(II)
mil)
14
15 Bank Address
16 BA0-BA1
17
18
Row Address
A0-A12
19
20 Auto Precharge
21 A10
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Pin Names
CK, CK
CKE
CS
RAS
CAS
WE
DQS (UDQS, LDQS)
A0–A12
BA0, BA1
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe (Bidirectional)
Address Inputs
Bank Select
V58C2256(804/404/164)SC*I Rev. 1.4 March 2007
DQ’s
DM (UDM, LDM)
VDD
VSS
VDDQ
VSSQ
NC
VREF
4
Data Input/Output
Data Mask
Power
(+2.5V and +2.6V for DDR400)
Ground
Power for I/O’s
(+2.5V and +2.6V for DDR400)
Ground for I/O’s
Not connected
Reference Voltage for Inputs
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