UPD4701A Datasheet PDF - NEC

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UPD4701A
NEC

Part Number UPD4701A
Description MOS INTEGRATED CIRCUIT
Page 16 Pages


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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4701A
INCREMENTAL ENCODER COUNTER
DESCRIPTION
The µPD4701A is a counter for an X, Y 2-axis incremental encoder. When a two-phase encoder signal is input
for the X and Y axes, direction discrimination and computation is performed, and count data is output in 8-bit parallel
form. In addition, a 3-contact-point input buffer is incorporated, which is useful for applications which use a pointing
device such as a mouse or track-ball. The CPU checks the switch input flag or count flag and reads the 12-bit count
data in two operations, one for the lower byte and one for the upper byte. The key input flag is output together with
the count data in the upper byte.
FEATURES
• X, Y 2-axis incremental encoder counter
• Counter input (Schmitt-triggered input)
X axis:
Y axis:
XA,
YA,
XB
YB
2-phase
2-phase
signal
signal

4-multiplication
count
method
used
• Counters: 12-bit binary up/down counters (2 sets, X & Y)
Reset value: 000H
• Count data output: 8-bit parallel latch output × 2 (including key input flag)
• On-chip 3-contact-point key input buffer circuit
• CMOS
• Single +5 V power supply
PIN CONFIGURATION (Top View)
PIN NAMES
XA, YA : A-phase inputs
XB, YB : B-phase inputs
RIGHT
LEFT Key inputs
MIDDLE
XA
XB
RESET X
YA
1
2
3
4
24 VDD
23 D7
22 D6
21 D5
CS
X/Y
U/L
D0 to 7
CF
SF
: Chip Select
: X/Y Counter Select
: Upper/Lower Byte Select
: Data outputs
: Count flag
: Count flag
RESET
RESET
X
Y

Counter
reset inputs
YB
RESET Y
RIGHT
LEFT
MIDDLE
SF
5
6
7
8
9
10
20 D4
19 D3
18 D2
17 D1
16 D0
15 CS
CF 11
14 X/Y
VSS 12
13 U/L
wwwD(O.Do.caDutm.aSNehnoet. eNtICo4U.-6.I9nC4e-7t3A3)03 (1st edition)
Date Published March 1997 P
Printed in Japan
© 1993



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µPD4701A
ORDERING INFORMATION
Part Number
µPD4701AC
µPD4701AGT
Package
24-pin plastic DIP (600 mil)
24-pin plastic SOP (375 mil)
BLOCK DIAGRAM
XA
XB
RESET X
Phase
Determination
and
Edge Detection
X-Axis Up/Down Counter
Data Multiplexer & Latch
RESET Y
YA
YB
Phase
Determination
and
Edge Detection
RIGHT
LEFT
MIDDLE
Button Input
Circuit
DATA MULTIPLEXER/LATCH BLOCK
Y-Axis Up/Down Counter
Count Flag
Circuit
Switch Flag
Circuit
CS
X/Y
U/L
D0-7
CF
SF
X-Axis Counter
12-Bit
Latch
STB
8
X/Y
U/L
Y-Axis Counter
12-Bit
Latch
STB
8
Data
8
Multiplexer
4
3-State
Buffer
OE
D0 - 7
Button Input
4-Bit
Latch
STB
CS
To Count Flag Circuit
2



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µPD4701A
PIN FUNCTIONS
CPU
interface
block
Mouse
interface
block
Pin Name
CS
X/Y
U/L
RESET X
RESET Y
D0 to 7
CF
SF
XA, XB
YA, YB
RIGHT
LEFT
MIDDLE
Input/Output
Input
Input
Input
Input
Output
(3-state)
Output
Output
Input
(Schmitt input)
Input
(Schmitt input)
Input
(Schmitt input)
Function
Chip Select input. “L” input activates outputs D0 to 7.
“H” input sets outputs D0 to 7 to high impedance.
Output data is latched on the fall edge of CS. “L” must be maintained during a
count data read.
Counter Select input. “L” input selects the X counter, and “H” input selects the
Y counter.
Byte Select input. “L” input selects the lower byte and “H” input selects the
upper byte, controlling data output.
Counter reset inputs. RESET X input resets the X counter, and RESET Y input
resets the Y counter. Both are active-“H”.
Bus for data output to the CPU. Outputs the byte data selected by the X/Y and
U/L inputs.
The data latched on the fall of CS is output.
Counter flag output. Set (= “L” output) when the X or Y counter changes while
CS = “H”. Reset (= “H” output) on the fall of CS. While CS = “L”, count flag
output is disabled and the “H” level is output.
Switch flag output. Becomes active (= “L” output) when the RIGHT, LEFT or
MIDDLE switch input is “L”.
X counter 2-phase signal input pins
Y counter 2-phase signal input pins
Key switch input pins. Key switch input are read as the high-order 4 bits of the
X counter and Y counter upper byte as the internal status.
Upper Byte
SF L R
M C11 C10 C9 C8
Key Input Status
Count Data
Power
supply
block
VDD
VSS
+5 V power supply connection pin
Ground pin
3



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µPD4701A
DESCRIPTION OF OPERATIONS
1. COUNT OPERATION
The µPD4701A executes an up-count and down-count by means of A & B 2-phase signals in the 12-bit up-down
counter. An up-count is performed when the A-phase signals (XA, YA) are phase-advanced, and a down-count is
performed when the B-phase signals (XB, YB) are phase-advanced. The edge of each signal is a count source. (4-
multiplication count method: see Fig. 1.)
Fig. 1 Count Operation Timing Chart
Forward (Up-Count)
Reverse (Down-Count)
(X, Y)A Input
Count Operation
(X, Y)B Input
12
3
45
43
21
0
This count operation is executed independently for the X axis (XA, XB) and Y axis (YA, YB). This operation is
initialized by reset input (RESET X, RESET Y) only.
In an up-count, the next value after FFFH is 000H, and in a down-count, the next value after 000H is FFFH.
2. OPERATION OF COUNT FLAG, CF
The count flag, CF, indicates that a count source (either XA, B or YA, B edge input) has occurred while the CS signal
is “H”, and is an active-low output. CF is reset (“H”) by CS signal “L” input. While CS = “L”, count flag output is
disabled and the “H” level is output.
Fig. 2 Count Flag Output Timing Chart
XA, B
YA, B
CF
CS
4
Count Flag Output Disabled in these Periods



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