( DataSheet : www.DataSheet4U.com )
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
8,388,608-WORDS × 4 BANKS × 16-BITS Network FCRAMTM
16,777,216-WORDS × 4 BANKS × 8-BITS Network FCRAMTM
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM913/05AMB is Network
FCRAMTM containing 536,870,912 memory cells. TC59LM913AMB is organized as 8,388,608-words × 4 banks × 16
bits, TC59LM905AMB is organized as 16,777,216-words × 4 banks × 8 bits. TC59LM913/05AMB feature a fully
synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. TC59LM913/05AMB can operate fast core cycle
compared with regular DDR SDRAM.
TC59LM913/05AMB is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
-50 -55 -60
tCK Clock Cycle Time (min)
CL = 3
CL = 4
tRC Random Read/Write Cycle Time (min)
tRAC Random Access Time (max)
IDD1S Operating Current (single bank) (max)
lDD2P Power Down Current (max)
lDD6 Self-Refresh Current (max)
• Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 5 ns minimum
Clock: 200 MHz maximum
Data: 400 Mbps/pin maximum
• Fast cycle and Short Latency
• Distributed Auto-Refresh cycle in 7.8 µs
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
CAS Latency = 3, 4
Burst Length = 2, 4
• Organization: TC59LM813AMB : 8,388,608 words × 4 banks × 16 bits
TC59LM805AMB : 16,777,216 words × 4 banks × 8 bits
• Power Supply Voltage VDD: 2.5 V ± 0.15V
VDDQ: 2.5 V ± 0.15 V
• 2.5 V CMOS I/O comply with SSTL-2 (half strength driver)
60Ball BGA, 1mm × 1mm Ball pitch
Notice : FCRAM is trademark of Fujitsu Limited, Japan.