TC59LM818DMB Datasheet PDF - Toshiba Semiconductor

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TC59LM818DMB
Toshiba Semiconductor

Part Number TC59LM818DMB
Description Network FCRAM
Page 30 Pages


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( DataSheet : www.DataSheet4U.com )
TC59LM818DMB-30,-33,-40
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
4,194,304-WORDS × 4 BANKS × 18-BITS Network FCRAMTM
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM818DMB is Network
FCRAMTM containing 301,989,888 memory cells. TC59LM818DMB is organized as 4,194,304-words × 4 banks × 18
bits. TC59LM818DMB feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM818DMB can operate fast core cycle compared with regular DDR SDRAM.
TC59LM818DMB is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
PARAMETER
TC59LM818DMB
-30 -33
CL = 4
4.0 ns
4.5 ns
tCK Clock Cycle Time (min)
CL = 5
3.33 ns
3.75 ns
CL = 6
3.0 ns
3.33 ns
tRC Random Read/Write Cycle Time (min)
20.0 ns
22.5 ns
tRAC Random Access Time (max)
20.0 ns
22.5 ns
IDD1S Operating Current (single bank) (max)
250 mA
235 mA
lDD2P Power Down Current (max)
60mA
55 mA
lDD6 Self-Refresh Current (max)
10 mA
10 mA
Fully Synchronous Operation
Double Data Rate (DDR)
Data input/output are synchronized with both edges of DS / QS.
Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and QS) is aligned to the crossings of CLK and CLK .
Fast clock cycle time of 3.0 ns minimum
Clock: 333 MHz maximum
Data: 666 Mbps/pin maximum
Quad Independent Banks operation
Fast cycle and Short Latency
Selectable Data Strobe
Distributed Auto-Refresh cycle in 3.9 µs
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
CAS Latency = 4, 5, 6
Burst Length = 2, 4
Organization: 4,194,304 words × 4 banks × 18 bits
Power Supply Voltage VDD: 2.5 V ± 0.125V
VDDQ: 1.4 V ~ 1.9 V
Low voltage CMOS I/O covered with SSTL-18 (Half strength driver) and HSTL
Package:
60Ball BGA, 1mm × 1mm Ball pitch (P-BGA60-0917-1.00AZ)
-40
5.0 ns
4.5 ns
4.0 ns
25 ns
25 ns
210 mA
50 mA
10 mA
Notice: FCRAM is trademark of Fujitsu limited, Japan.
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2003-02-28 1/55



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PIN NAMES
PIN
A0~A14
BA0, BA1
DQ0~DQ17
CS
FN
PD
CLK, CLK
DS / QS
VDD
VSS
VDDQ
VSSQ
VREF
NC
NAME
Address Input
Bank Address
Data Input/Output
Chip Select
Function Control
Power Down Control
Clock Input
Write/Read Data Strobe
Power (+2.5 V)
Ground
Power (+1.5 V, +1.8 V)
(for DQ buffer)
Ground
(for DQ buffer)
Reference Voltage
Not Connected
TC59LM818DMB-30,-33,-40
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm
x18
123456
A Index VSS DQ17
B DQ16 VSSQ
C DQ15 VDDQ
D DQ14 DQ13
E DQ12 VSSQ
F DQ11 VDDQ
G DQ10 VSSQ
H DQ9 DS
J VREF VSS
K CLK CLK
L A12 PD
M A11 A9
N A8 A7
P A5 A6
R VSS A4
DQ0 VDD
VDDQ DQ1
VSSQ DQ2
DQ4 DQ3
VDDQ DQ5
VSSQ DQ6
VDDQ DQ7
QS DQ8
VDD A14
FN A13
CS NC
BA1 BA0
A0 A10
A2 A1
A3 VDD
: Depopulated Ball
2003-02-28 2/55



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BLOCK DIAGRAM
TC59LM818DMB-30,-33,-40
CLK
CLK
PD
CS
FN
DLL
CLOCK
BUFFER
To each block
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A0~A14
BA0, BA1
ADDRESS
BUFFER
MODE
REGISTER
UPPER ADDRESS
LATCH
LOWER ADDRESS
LATCH
REFRESH
COUNTER
BURST
COUNTER
WRITE ADDRESS
LATCH/
ADDRESS
COMPARATOR
BANK #3
BANK #2
BANK #1
BANK #0
MEMORY
CELL ARRAY
COLUMN DECODER
READ
DATA
BUFFER
WRITE
DATA
BUFFER
DS
QS
DQ BUFFER
DQ0~DQ17
Note: The TC59LM818DMB configuration is 4 Bank of 32768 × 128 × 18 of cell array with the DQ pins numbered DQ0~DQ17.
2003-02-28 3/55



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ABSOLUTE MAXIMUM RATINGS
TC59LM818DMB-30,-33,-40
SYMBOL
PARAMETER
RATING
UNIT
NOTES
VDD Power Supply Voltage
0.3~ 3.3
V
VDDQ
Power Supply Voltage (for DQ buffer)
0.3~VDD+ 0.3
V
VIN Input Voltage
0.3~VDD+ 0.3
V
VOUT
Output and DQ pin Voltage
0.3~VDDQ + 0.3
V
VREF
Input Reference Voltage
0.3~VDD+ 0.3
V
Topr Operating Temperature (Ambient)
0~70
°C
Tstg Storage Temperature
55~150
°C
Tsolder
Soldering Temperature (10 s)
260 °C
PD Power Dissipation
2W
IOUT
Short Circuit Output Current
±50 mA
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1) (TCASE = 0 ~ 85°C)
SYMBOL
PARAMETER
MIN
VDD
VDDQ
VREF
VIH (DC)
VIL (DC)
VICK (DC)
VID (DC)
VIH (AC)
VIL (AC)
VID (AC)
VX (AC)
VISO (AC)
Power Supply Voltage
2.375
Power Supply Voltage (for DQ buffer)
1.4
Reference Voltage
Input DC High Voltage
Input DC Low Voltage
VDDQ/2 × 95%
VREF + 0.125
0.1
Differential Clock DC Input Voltage
0.1
Differential Input Voltage.
CLK and CLK inputs (DC)
0.4
Input AC High Voltage
Input AC Low Voltage
VREF + 0.2
0.1
Differential InputVoltage.
CLK and CLK inputs (AC)
0.55
Differential AC Input Cross Point Voltage VDDQ/2 0.125
Differential Clock AC Middle Level
VDDQ/2 0.125
TYP.
2.5
VDDQ/2
MAX
UNIT NOTES
2.625
1.9
VDDQ/2 × 105%
VDDQ + 0.2
VREF 0.125
VDDQ + 0.1
V
V
V
V
V
V
2
5
5
10
VDDQ + 0.2 V 7, 10
VDDQ + 0.2 V 3, 6
VREF 0.2 V 4, 6
VDDQ + 0.2 V 7, 10
VDDQ/2 + 0.125
VDDQ/2 + 0.125
V
V
8, 10
9, 10
2003-02-28 4/55



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