TC1550 Datasheet PDF - Supertex

www.Datasheet-PDF.com

TC1550
Supertex

Part Number TC1550
Description N- and P-Channel Enhancement-Mode Dual MOSFET
Page 5 Pages


TC1550 datasheet pdf
Download PDF
TC1550 pdf
View PDF for Mobile

No Preview Available !

TC1550
N- and P-Channel
Enhancement-Mode Dual MOSFET
Features
500V breakdown voltage
Independent N- and P-channels
Electrically isolated N- and P-channels
Low input capacitance
Fast switching speeds
Free from secondary breakdowns
Low input and output leakage
Applications
High voltage pulsers
Amplifiers
Buffers
Piezoelectric transducer drivers
General purpose line drivers
General Description
The Supertex TC1550 consists of a high voltage N-channel and
P-channel MOSFET in an 8-Lead SOIC package. This is an
enhancement-mode (normally-off) transistor utilizing an advanced
vertical DMOS structure and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces a device with
the power handling capabilities of bipolar transistors and with the
high input impedance and positive temperature coefficient inherent
in MOS devices. Characteristic of all MOS structures, this device
is free from thermal runaway and thermally induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Ordering Information
Package Option
Device
8-Lead SOIC
4.90x3.90mm body
1.75mm height (max)
1.27mm pitch
TC1550
TC1550TG-G
-G indicates package is RoHS compliant (‘Green’)
BVDSS/BVDGS
N-Channel
(V)
P-Channel
(V)
500 -500
RDS(ON)
(Max)
N-Channel
(Ω)
P-Channel
(Ω)
60 125
Pin Configuration
DP
DP
DN
DN
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±20V
Operating and storage temperature -55°C to + 150°C
Soldering temperature*
300°C
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
GP
SP
GN
SN
8-Lead SOIC (TG)
(top view)
Product Marking
YYWW
C1550
LLLL
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
8-Lead SOIC (TG)
1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com



No Preview Available !

TC1550
N-Channel Electrical Characteristics (TA = 25°C unless otherwise specified)
Sym Parameter
Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage
500 -
-
V VGS = 0V, ID = 1.0mA
VGS(th) Gate threshold voltage
2.0 - 4.0
V VGS = VDS, ID =1.0mA
ΔVGS(th) Change in VGS(th) with temperature
- -3.8 -5.0 mV/OC VGS = VDS, ID = 1.0mA
IGSS Gate body leakage current
-
- 100
nA VGS = ±20V, VDS = 0V
IDSS Zero gate voltage drain current
- - 10 µA VGS = 0V, VDS = Max Rating
-
-
1.0
mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
ID(ON) On-state drain current
- 100
150 350
-
-
mA VGS = 5.0V, VDS = 25V
VGS = 10V, VDS = 25V
RDS(ON)
Static drain-to-source
on-state resistance
- 45 -
- 40 60
Ω VGS = 5.0V, ID = 50mA
VGS = 10V, ID = 50mA
ΔRDS(ON) Change in RDS(ON) with temperature
- 1.0 1.7 %/OC VGS = 10V, ID = 50mA
GFS Forward transconductance
50 100 - mmho VDS = 25V, ID =50mA
CISS
COSS
CRSS
Input capacitance
Common source output capacitance
Reverse transfer capacitance
- 45 55
- 8.0 10
- 2.0 5.0
VGS = 0V,
pF VDS = 25V,
f = 1.0MHz
td(ON)
tr
td(OFF)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
- - 10
- - 15
VDD = 25V,
-
- 10
ns ID = 150mA,
RGEN = 25Ω
- - 10
VSD Diode forward voltage drop
- 0.8 -
V VGS = 0V, ISD = 500mA
trr Reverse recovery time
- 300 -
ns VGS = 0V, ISD = 500mA
Notes:
1. All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.)
2. All AC parameters sample tested.
N-Channel Switching Waveforms and Test Circuit
10V
Input
0V
10%
VDD
Output
0V
t(ON)
td(ON)
tr
10%
90%
90%
t(OFF)
td(OFF)
tf
10%
90%
Pulse
Generator
RGEN
Input
VDD
RL
OUTPUT
D.U.T.
1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
2



No Preview Available !

TC1550
P-Channel Electrical Characteristics (TA = 25°C unless otherwise specified)
Sym Parameter
Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage
-500 -
-
V VGS = 0V, ID = -1.0mA
VGS(th) Gate threshold voltage
-2.0 - -4.5
V VGS = VDS, ID = -1.0mA
ΔVGS(th) Change in VGS(th) with temperature
- 3.5 6.0 mV/OC VGS = VDS, ID = -1.0mA
IGSS Gate body leakage current
-
- 100
nA VGS = ±20V, VDS = 0V
IDSS Zero gate voltage drain current
-
- -10
µA VGS = 0V, VDS = Max Rating
-
-
-1.0
mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
ID(ON) On-state drain current
- -90
-100 -240
-
-
mA VGS = -5.0V, VDS = -25V
VGS = -10V, VDS = -25V
RDS(ON)
Static drain-to-source
on-state resistance
- 85 -
- 80 125
Ω VGS = -5.0V, ID = -5.0mA
VGS = -10V, ID = -10mA
ΔRDS(ON) Change in RDS(ON) with temperature
- 0.85 -
%/OC VGS = -10V, ID = -10mA
GFS Forward transconductance
25 40 - mmho VDS = -25V, ID = -10mA
CISS
COSS
CRSS
Input capacitance
Common source output capacitance
Reverse transfer capacitance
- 40 70
- 10 20
- 3.0 10
VGS = 0V,
pF VDS = -25V,
f = 1.0MHz
td(ON)
tr
td(OFF)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
- 5.0 10
- 8.0 10
- 8.0 15
- 5.0 16
VDD = -25V,
ns ID = -100mA,
RGEN = 25Ω
VSD Diode forward voltage drop
- -0.8 -1.5
V VGS = 0V, ISD = -100mA
trr Reverse recovery time
- 200 -
ns VGS = 0V, ISD = -100mA
Notes:
1. All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.)
2. All AC parameters sample tested.
P-Channel Switching Waveforms and Test Circuit
0V
Input
-10V
0V
Output
VDD
10%
t(ON
td(O)N)
90%
tr
t(OFF)
td(OFF) tf
90% 90%
10%
10%
Pulse
Generator
RGEN
Input
D.U.T.
RL
VDD
OUTPUT
1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
3



No Preview Available !

Typical Application Circuit
+12V
3.3V CMOS
Logic Inputs
VDD1 VDD2 VH
OE
0.47µF 15V
INA
OUTA
10nF
250V
INB
OUTB
10nF
250V
GND VSS1 VSS2 VL
15V
Supertex
MD1213K6
TC1550
+250V
Piezoelectric
Transducer
Supertex
TC1550TG
-250V
Block Diagram
SN 1
N-Channel
GN 2
SP 3
P-Channel
GP 4
8 DN
7 DN
6 DP
5 DP
1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
4



TC1550 datasheet pdf
Download PDF
TC1550 pdf
View PDF for Mobile


Related : Start with TC155 Part Numbers by
TC1550 N- and P-Channel Enhancement-Mode Dual MOSFET TC1550
Supertex
TC1550 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact