TAA2008 Datasheet PDF - Tripath Technology

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TAA2008
Tripath Technology

Part Number TAA2008
Description DIGITAL AUDIO AMPLIFIER USING DIGITAL POWER PROCESSING
Page 18 Pages


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Tripath Technology, Inc. - Technical Information
TA A 2 0 0 8
STEREO 9W (8) CLASS-T™ DIGITAL AUDIO AMPLIFIER USING
DIGITAL POWER PROCESSING™ TECHNOLOGY
TECHNICAL INFORMATION
Revision 1.0 – May 2006
GENERAL DESCRIPTION
The TAA2008 is a 9W/ch continuous average two-channel Class-T Digital Audio Power Amplifier IC
using Tripath’s proprietary Digital Power Processing™ technology. The TAA2008, in a QFN package,
along with extremely high efficiency, allows for a very compact amplifier design. Class-T amplifiers
offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.
APPLICATIONS
FEATURES
LCD TV’s
LCD Monitors
Plasma TV’s
Computer/PC Multimedia
Battery Powered Systems
BENEFITS
Fully integrated solution with FETs
Compact packaging and board design
Reduced system cost with no heat sink
Dramatically improves efficiency versus Class-
AB
Signal fidelity equal to high quality linear
amplifiers
High dynamic range compatible with digital
media such as CD, DVD, and Internet audio
Capable of driving a wide range of load
impedances
TYPICAL PERFORMANCE
THD+N versus Output Power
10
VDD = 12V
5
f = 1kHz
ABVW=
12V/V
= 22Hz
-
20kHz(AES17)
Class-T architecture
Single Supply Operation
“Audiophile” Quality Sound
0.025% THD+N @ 5W, 8
0.1% IHF-IM @ 1W, 8
6.3W @ 8, 0.1% THD+N
3.5W @ 16, 0.1% THD+N
High Power
14.25W @ 6, 10% THD+N
9W @ 8, 10% THD+N
5W @ 16, 10% THD+N
Extremely High Efficiency
89% @ 5W, 16
86% @ 9W, 8
Dynamic Range = 98.5 dB
Mute and Sleep modes
Improved turn-on & turn-off pop
suppression
Over-current protection with automatic
restart circuit
Over-temperature protection
Space saving 32-pin 8mm x 8mm x 1mm
QFN package with exposed pad
2
RL =16
RL =8
RL =6RL =4
1
OAOUT2 1
24 AGND1
0.5
INV2 2
23 V5D
BIASCAP 3
22 DCAP1
0.2
AGND3
SLEEP
4
5
21 DCAP2
20 5VGEN
0.1
FAULT
PGND2
6
7
19 CPUMP
18 PGND1
0.05
DGND 8
17 VDDA
0.02
0.01
1
1
2 3 4 5 6 7 8 9 10
Output Power (W)
20
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A B S O L U T E M A X I M U M R A T I N G S (Note 1)
SYMBOL
VDD
V5
SLEEP
MUTE
TSTORE
TA
TJ
ESDHB
ESDMM
PARAMETER
Supply Voltage
Input Section Supply Voltage
SLEEP Input Voltage
MUTE Input Voltage
Storage Temperature Range
Operating Free-air Temperature Range
Junction Temperature
ESD Susceptibility – Human Body Model (Note 2)
ESD Susceptibility – Machine Model (Note 3)
Value
16
6.0
-0.3 to 6.0
-0.3 to V5+0.3
-40 to 150
0 to 70
150
2000
200
UNITS
V
V
V
V
°C
°C
°C
V
V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Human body model, 100pF discharged through a 1.5Kresistor.
Note 3: Machine model, 220pF – 240pF discharged through all pins.
O P E R A T I N G C O N D I T I O N S (Note 4)
SYMBOL
VDD
VIH
VIL
PARAMETER
Supply Voltage (Note 5)
High-level Input Voltage (MUTE, SLEEP)
Low-level Input Voltage (MUTE, SLEEP)
MIN.
8.5
3.5
TYP.
12
MAX.
14.0
1
UNITS
V
V
V
Note 4: Recommended Operating Conditions indicate conditions for which the device is functional. See
Electrical Characteristics for guaranteed specific performance limits.
Note 5: Operation above 13.2V requires the use of low and high side schottky diodes as well as 220uF for
CSW. See the Application Section for additional information
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
θJA Junction-to-ambient Thermal Resistance (note 6)
VALUE UNITS
22 °C/W
Note 6: The θJA value is based on the exposed pad being soldered down to the printed circuit board. The
exposed pad must be soldered to an exposed copper area on the printed circuit board for proper thermal
and electrical performance.
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E L E C T R I C A L C H A R A C T E R I S T I C S (Note 7)
See Test/Application Circuit. Unless otherwise specified, VDD = 12V, f = 1kHz, Measurement
Bandwidth = 20kHz, RL = 8, TA = 25 °C, package exposed pad soldered to the printed circuit
board.
SYMBOL
PARAMETER
PO Output Power
(Continuous Average/Channel)
IDD,MUTE
IDD, SLEEP
Iq
THD + N
IHF-IM
SNR
CS
Mute Supply Current
Sleep Supply Current
Quiescent Current
Total Harmonic Distortion Plus
Noise
IHF Intermodulation Distortion
Signal-to-Noise Ratio
Channel Separation
PSRR
η
VOFFSET
VOH
VOL
eOUT
Power Supply Rejection Ratio
Power Efficiency
Output Offset Voltage
High-level output voltage
(FAULT & OVERLOAD)
Low-level output voltage
(FAULT & OVERLOAD)
Output Noise Voltage
CONDITIONS
THD+N = 0.1%
RL = 6
RL = 8
RL = 16
THD+N = 10%
RL = 6
RL = 8
RL = 16
VDD = 13.2V, THD+N=10%
RL = 6
RL = 8
RL = 16
MUTE = VIH
SLEEP = VIH
VIN = 0 V
PO = 5W/Channel
19kHz, 20kHz, 1:1 (IHF)
A-Weighted, POUT = 9W, RL = 8
f = 1 kHz
20 Hz < f < 20 kHz
VDD = 9V to 13.2V
Vripple = 100mVrms, f=1kHz
POUT = 5W/Channel, RL = 16
No Load, MUTE = Logic Low
A-Weighted, input AC grounded
MIN.
TBD
TYP.
8
6.3
3.5
12
9
5
MAX.
UNITS
W
W
W
W
W
W
14.25
12
6.3
31
0.25
61
0.022
36
2
75
0.1 0.5
98.5
85
50 60
65 75
65
89
50 150
3.5
1
100 150
W
W
W
mA
mA
mA
%
%
dB
dB
dB
dB
dB
%
mV
V
V
µV
Note 7: Minimum and maximum limits are guaranteed but may not be 100% tested.
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Tripath Technology, Inc. - Technical Information
PIN DESCRIPTION
Pin
1, 29
2, 30
Function
OAOUT2, OAOUT1
INV2, INV1
3
4, 24,
27
5
BIASCAP
AGND3, AGND1,
AGND2
SLEEP
6 FAULT
7, 18
8
10, 12;
15, 13
11, 14
17
19
20
PGND2, PGND1
DGND
OUTP2 & OUTM2;
OUTP1 & OUTM1
VDD2, VDD1
VDDA
CPUMP
5VGEN
21,22
DCAP2, DCAP1
23, 28
25
26
31
9, 16, 32
V5D, V5A
REF
OVERLOADB
MUTE
NC
Description
Input stage output pins.
Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with
approximately 2.4VDC bias.
Input stage bias voltage (approximately 2.4VDC).
Analog Ground
When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
Power Grounds (high current)
Digital Ground. Connect to AGND locally (near the TAA2008).
Bridged output pairs
Supply pins for high current H-bridges, nominally 12VDC.
Analog 12VDC. Connect to same supply as VDD1 and VDD2.
Charge pump output (nominally 10V above VDDA)
Regulated 5VDC source used to supply power to the input section (pins 23 and
28).
Charge pump switching pins. DCAP1 (pin 22) is a free running 300kHz square
wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 21) is level
shifted 10 volts above DCAP1 (pin 22) with the same amplitude (12Vpp nominal),
frequency, and phase as DCAP1.
Digital 5VDC, Analog 5VDC
Internal reference voltage; approximately 1.0 VDC.
A logic low output indicates the input signal has overloaded the amplifier.
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. This pin should be tied to GND if not used.
Not connected. Not bonded internally.
TAA2008 PINOUT
32-pin QFN
(Top View)
OAOUT2
INV2
BIASCAP
AGND3
SLEEP
FAULT
PGND2
DGND
1
2
3
4
5
6
7
8
24 AGND1
23 V5D
22 DCAP1
21 DCAP2
20 5VGEN
19 CPUMP
18 PGND1
17 VDDA
4 TAA2008 –KLi/1.0/05.06



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