STEL-1175 Datasheet PDF - Intel

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STEL-1175
Intel

Part Number STEL-1175
Description 32-Bit Resolution CMOS Phase Modulated Numerically Controlled Oscillator
Page 14 Pages


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STEL-1175
Data Sheet
STEL-1175+125
(125 MHz)
32-Bit Resolution CMOS
Phase Modulated
Numerically
Controlled Oscillator
R



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FEATURES
s VERY HIGH CLOCK FREQUENCY
- 125 MHz MAXIMUM OVER FULL
MILITARY TEMPERATURE RANGE
s HIGH FREQUENCY RESOLUTION
- 32-BITS, 30 milli-Hz @ 125 MHz
s WIDE OUTPUT BANDWIDTH
- 0 TO 50 MHz @ 125 MHz CLOCK
s SHORT CLOCK TO OUTPUT DELAY FOR
DIRECT CLOCK CONNECT TO 1175 AND
DAC
s PRECISION PHASE MODULATION
www.DataSheet4U.c-om12-BITS, 0.09° RESOLUTION, CAN BE
USED FOR LINEAR PM OR PULSE-
SHAPED PSK
s SINE OR COSINE SIGNAL GENERATION
- 12-BIT OUTPUTS
s HIGH SPECTRAL PURITY
ALL SPURS < -75 dBc
(AT DIGITAL OUTPUT)
s MICROPROCESSOR COMPATIBLE
INPUTS
s LOW POWER DISSIPATION
s 68 PIN PLCC PACKAGE
(COMMERCIAL TEMPERATURE RANGE)
s 68 PIN CERAMIC LCC PACKAGE
(MILITARY TEMPERATURE RANGE)
BLOCK DIAGRAM
TYPICAL APPLICATIONS
s FREQUENCY SYNTHESIZERS
s PSK MODULATORS
s DIGITAL SIGNAL PROCESSORS
s FAST HOPPED FREQUENCY SOURCES
FUNCTIONAL DESCRIPTION
The STEL-1175 Modulated Numerically Controlled
Oscillator (MNCO) uses digital techniques to provide a
cost-effective solution for low noise signal sources. The
device can operate at clock frequency up to 125 MHz and
provides high frequency resolution and high spectral purity
of outputs up to 50 MHz. The STEL-1175 also features
phase modulation at rates up to 25% of the clock
frequency. The 12-bit output can be selected to be a sine
or cosine function, so that two STEL-1175 NCOs can be
used to generate quadrature signals with independent
phase modulation. Two independent frequency control
registers are provided, allowing high speed frequency
hopping or binary FSK at rates to 25% of the clock
frequency. The device combines low power 0.5µ CMOS
technology with a unique architectural design resulting in
a power efficient, high-speed sinusoidal waveform
generator able to achieve fine tuning resolution and high
spectral purity at clock frequencies up to 125 MHz. The
NCO is designed to provide a simple interface to an 8-bit
microprocessor bus.
PHLCK
PHLD
FRLD
PHSEL
ADDR 4
CSEL
WRSTB
ADDRESS
SELECT
LOGIC
DATA
8
PHASE
MOD
CONTROL
32
-PHASE
BUFFER
REGISTERS 32
MUX
PHASE
OUTPUT
12 PHASE
REGISTER
12
12 PSYNC
-PHASE 32
REGISTER
32
32-BIT
PHASE
ACCUMU-
LATOR
13 PHASE
ALU
13
SIN/COS 12
OUT
LUT
FRSEL
CIN
CLOCK
SINE
ROUND
RESET
TO ALL REGISTERS
COUT
FSYNC
TCP 39074-12/17/98
STEL-1175+125
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The NCO maintains a record of phase which is accurate to
32 bits. At each clock cycle, the number stored in the 32-
bit -Phase register is added to the previous value of the
phase accumulator. The number in the phase accumulator
represents the current phase of the synthesized sine and
cosine functions. The number in the -Phase register
represents the phase change for each cycle of the clock.
This number is directly related to the output frequency by
the following:
fo=
fc x -Phase
232
where:
www.DataSheet4U.caonmd:
fo is the frequency of the output signal
fc is the clock frequency.
PIN CONFIGURATION
Package: 68 pin PLCC
Thermal coefficient, θja = 35°/W
The sine and cosine functions are generated from the 13
most significant bits of the phase accumulator. The
frequency of the NCO is determined by the number stored
in the -Phase Register, which may be programmed by an
8-bit microprocessor.
The NCO generates a sampled sine wave where the
sampling function is the clock. The practical upper limit of
the NCO output frequency is about 40% of the clock
frequency due to spurious components that are created by
sampling. Those components are at frequencies greater
than half the clock frequency and can be removed by
filtering.
The phase noise of the NCO output signal may be
determined from the phase noise of the clock signal input
and the ratio of the output frequency to the clock
Package: 68 pin CLDCC
Thermal coefficient, θja = 34°C/W
PIN CONNECTIONS
1 PHASE1
2 PHASE2
3 PHASE3
4 PHASE4
5 PHASE5
6 DATA0
7 DATA1
8 DATA2
9 DATA3
10 DATA4
11 DATA5
12 DATA6
13 DATA7
14 PHASE6
15 PHASE7
16 PHASE8
17 PHASE9
18 PHASE10
19 PHASE11
20 WRSTB
21 PHSEL
22 I.C.
23 RESET
24 ROUND
25 SINE
26 FRSEL
27 VDD
28 VSS
29 FRLD
30 COUT
31 CSEL
32 PHLD
33 PHCLK
34 VSS
35 VDD
36 OUT0(LSB)
37 OUT1
38 OUT2
39 OUT3
40 OUT4
41 N.C.
42 VSS
43 VDD
44 OUT5
45 OUT6
46 OUT7
47 OUT8
48 OUT9
49 OUT10
50 OUT11
51 VSS
52 VDD
53 N.C.
54 N.C.
55 N.C.
56 FSYNC
57 PSYNC
58 ADDR0
59 VSS
60 VDD
61 ADDR1
62 ADDR2
63 ADDR3
64 CLOCK
65 CIN
66 VDD
67 VSS
68 PHASE0
Notes: 1. I.C. denotes Internal Connection. These pins must be left unconnected. Do not use for vias.
2. Connect all unused inputs to Vss, leave unused outputs unconnected.
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frequency. This ratio squared times the phase noise power
of the clock specified in a given bandwidth is the phase
noise power that may be expected in that same bandwidth
relative to the output frequency.
The NCO achieves its high operating frequency by making
extensive use of pipelining in its architecture. The pipeline
delays within the NCO represent 19 clock cycles. The dual
-Phase registers used in the STEL-1175 allow the
frequency to be updated as rapidly as every fourth clock
cycle, i.e. at 25% of the clock frequency. The pipeline delay
associated with the phase modulator is only 12 clock cycles,
www.DataSheesti4nUc.ecotmhe phase modulating function is at the output of the
accumulator. The phase modulation may also be changed
as rapidly as every fourth clock cycle, at 25% of the clock
frequency, resulting in a maximum modulation rate of 30
MHz with a clock frequency of 125 MHz. Note that when
a phase or frequency change occurs at the output the
change is instantaneous, i.e., it occurs in one clock cycle,
with complete phase coherence.
FUNCTION BLOCK DESCRIPTION
ADDRESS SELECT LOGIC BLOCK
This block controls the writing of data into the device via
the DATA7-0 inputs. The data is written into the device on
the rising edge of the WRSTB input, and the register into
which the data is written is selected by the ADDR3-0 inputs.
The CSEL input can be used to selectively enable the
writing of data from the bus.
PHASE MODULATION CONTROL BLOCK
This block includes the Phase Modulation Buffer Register
and controls the source of the phase modulation (PM) data
by means of the PHSEL input. When this signal is low,
data from the DATA7-0 and ADDR3-0 inputs is written
directly into the Phase ALU after a falling edge on the
PHLD input. When PHSEL is high, data is written into
the Phase Modulation Buffer Register from the DATA7-0
bus on the rising edge of the WRSTB input. The data will
then be transferred into the Phase ALU after the next
falling edge of PHLD. The source of the PM data applied
to the Phase ALU will be the Phase Buffer Register in this
mode.
-PHASE BUFFER REGISTERS A & B BLOCK
The two -Phase Buffer Registers are used to temporarily
store the -Phase data written into the device. This allows
the data to be written asynchronously as four bytes per 32-
bit -Phase word. The data is transferred from these
registers into the -Phase Register after a falling edge on
the FRLD input.
STEL-1175+125
MUX BLOCK
This block is used to select which -Phase Buffer Register
is used as the source of frequency data for the -Phase
Register, by means of the FRSEL input.
-PHASE REGISTER BLOCK
This block controls the updating of the -Phase word used
in the Accumulator. The frequency data from the Mux
Block is loaded into this block after a falling edge on the
FRLD input. This block also generates the FSYNC
output, which indicates the instant at which any frequency
change made at the inputs affects the OUT11-0 signals.
PHASE ACCUMULATOR BLOCK
This block forms the core of the NCO function. It is a
high-speed, pipelined, 32-bit parallel accumulator,
generating a new sum in every clock cycle. A carry input
(the CIN input) allows the resolution of the accumulator
to be expanded by means of an auxiliary NCO or phase
accumulator. The overflow signal is discarded (and is
available at the COUT pin), since the required output is
the modulo(232) sum only. This represents the modulo(2þ)
phase angle.
PHASE ALU BLOCK
The Phase ALU performs the addition of the PM data to
the Phase Accumulator output. The PM data word is 12
bits wide, and this is added to the 13 most significant bits
from the Phase Accumulator to form the modulated phase
used to address the lookup table. This block also generates
the PSYNC output, which indicates the instant at which
any phase change made at the inputs affects the OUT11-0
signals.
SINE/COSINE LOOKUP TABLE BLOCK
This block is the sine/cosine memory. The 13 bits from
the Phase ALU are used to address this memory to
generate the 12-bit OUT11-0 outputs. The output will be a
sine signal when the SINE input is high, and will be a
cosine signal when this input is low.
PHASE OUTPUT REGISTER BLOCK
The twelve most significant bits from the Phase ALU
Block are latched into the Phase Output Register on the
rising edges of the PHCLK input. The output of this
register is available on the PHASE11-0 pins.
INPUT SIGNALS
RESET
The RESET input is asynchronous and active low, and
clears all the registers in the device. When RESET goes
low, all registers are cleared within 20 nsecs, and normal
operation will resume after this signal returns high. The
data on the OUT11-0 bus will then be invalid for 6 rising
4



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STEL-1175 32-Bit Resolution CMOS Phase Modulated Numerically Controlled Oscillator STEL-1175
Intel
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