ST7282A5 - ST7282B5 - ROM FROM EPROM
1.1 Quick Reference
The ST7282A5/B5 is a 32K ROM version of the
ST72 family, using the ST72CORE and N-Well
It is derived from EPROM M4 version replacing
EPROM by ROM.
Two different commercial products are supported
by this device : ST7282A5 (no LCD driver) func-
tionnality described in specification SD70KL1618
ed. F) and ST7282B5 (LCD driver) functionnality
described in specification 96096 ed. B).
It contains an LCD controller/driver with 20 seg-
ment and 16 backplane outputs able to drive up to
20 x 16 = 320 segments.
The LCD control logic reads automatically data
from the LCD-RAM independently from the
Further it contains up to 62 I/O pins, 24 of them
can be used as analog inputs to the 8 bit analog-
digital converter. Each digital I/O pin can individu-
ally be defined by software to work in one of the
following modes: open-drain output, push pull out-
put, input, input with pull-up (23 pins only) or inter-
rupt input with pull up (23 pins only). 3 of the digital
I/O pins serve as interface to the SIO. On pin PA4
the pull-up resistor is desactivated.
Port pins PD, PE, PF, PG and PH are multiplexed
with LCD Segment and backplane pins.
A 512 byte EEPROM for non volatile storage of
data is available. The programming voltage for
that device is generated on chip without external
components. So no extra supply is necessary. 16
bytes are protected against external readout.
One interrupt vector is connected to the I/O ports.
Five more interrupt vectors are available for the
timer, the ADC, the serial I/O interface and the
Group & Block Sync module (2). The watchdog
can be set by the user in 64 increments from
2.8msec to 182msec ( fOSC = 8.55 MHz ).
A synchronous 8 bit serial interface for serial data
IN/OUT is also implemented.
RDS signals can be decoded with the help of RDS
filter, RDS demodulator and Group & Block Sync
The values below substitute the corresponding values in the specifications of dedicated functions.
1.2.1 Absolute maximum ratings
Output voltage Seg+COM
( VDD - VSS )
(VLCD - VSS)
-0.3 ... +7V
VSS-0.3V ... VDD+0.3V
-10 ... +10mA
-10 ... + 10mA
-55 ... +125°C
-40 ... +85°C
VDD ... 7V
VSS-0.3V ... VLCD+0.3V
VDDA, Pin 52 - Class C
1.2.2 Recommended operating conditions
Supply votage difference
(VDD - VSS)
(VDD, VDDP, VDDA)
(VSS, VSSP, VSSA)
4.5 ... 5.5V
The maximum accumulated current of all I/O pins
should not exceed 40 mA for VDDP and 40 mA for
* except LCD pins
** MIL 883B Mode, 100pF through 1.5k
March 26, 1997