ST7282 Datasheet PDF - ST Microelectronics

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ST7282
ST Microelectronics

Part Number ST7282
Description ROM from EPROM
Page 23 Pages


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ST7282A5 - ST7282B5
s ST72-Core
s Controller/Driver for max. 20 × 16, 28 × 8
or 32 × 4
s LCD segments (ST7LCD4)
s 56 bytes LCD-RAM
s 864 bytes data RAM
s 512 bytes EEPROM (eep2a)
s 32Kbytes program ROM
s 24 digital I/O (ST7 IO3) with pull up,
interrupt input, analog input, push-pull/
open drain output
s 36 LCD/IO combi pins (ST7 LCIO1) with
pull-up, interrupt input, push-pull, open
drain output, LCD output
s 16 bit reload timer (ST7TIM4)
s Watchdog Timer (ST7 WD2)
s 8 bit synchronous serial I/O (ST7SIO)
s 8 bit A/D Converter (ST7ADC2)
s RDS Demodulator (ST7 RDS BD)
ROM FROM EPROM
PRELIMINARY DATASHEET
s Group & Block Sync Module for RDS (ST7
RDS GB)
s RDS filter (ST7 RDS FI)
s LCD Synchro IN / Out
s System Frequency 8.55 MHz
n
n
Family
ST7
Issuer Ref.
PG-RO
Chrono
97115
7282A5B5
March 26, 1997
Previous Ref
Edition
Target C
Page 1/23



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ST7282A5 - ST7282B5 - ROM FROM EPROM
1 GENERAL DESCRIPTION
Figure 1. Block Diagram
S 1 6/P D 7
S 1 5/P D 6
S 1 4/P D 5
S 1 3/P D 4
S 1 2/P D 3
S 1 1/P D 2
S 1 0/P D 1
S9/PD 0
S8/PF 7
S7/PF 6
S6/PF 5
S5/PF 4
S4/PF 3
S3/PF 2
S2/PF 1
S1/PF 0
B P 1 6 /S 0 /P G 7
BP15/S-1/PG 6
BP14/S-2/PG 5
BP13/S-3/PG 4
BP12/S-4/PG 3
BP11/S-5/PG 2
BP10/S-6/PG 1
BP 9/S -7/PG 0
PORT C
ST 7 IO3
PORT B
ST 7 IO3
EEPR OM 512
W A TCHDOG
ST7 WD2
T IM ER 16 bit
ST 7 T IM 4
AD C
ST7 ADC2
SIO
RAM 864
32K R OM
RDS DEMOD.
ST7 RDS BD
LCD RAM
5 6B y te
ST72 CORE
GR P & BLK S YNC
ST7 RDS GB
R D S Filter
ST7 RDS FI
O SCILLAT O R
ST 7 O SCILLATO R
PORT H
ST 7 LCIO
LCD CONTROL
ST7 LC D4
S eg. D rv./Port E
ST 7 LCIO
PA 0/C P 1/A IN
PA 1/C P 2/A IN
PA 2/A IN
PA 3/A IN
PA 4/A IN
PA 5/A IN
PA 6/A IN
PA 7/A IN
RD S CO MP/PE4/S21
VD D
VSS
VPP/T EST
RE SE T
MPX
RD S FIL
RDS REF
O SCIN
O SCO U T/ST OP
8 .55M H z
S 2 2/P E 5
S2 1/P E4 /R D S C OM P
O sc - O ptio n
n
n
n
Family
ST7
Issuer Ref.
PG-RO
Chrono
97115
7282A5B5
March 26, 1997
Previous Ref
Edition
Target C
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ST7282A5 - ST7282B5 - ROM FROM EPROM
1.1 Quick Reference
The ST7282A5/B5 is a 32K ROM version of the
ST72 family, using the ST72CORE and N-Well
technology.
It is derived from EPROM M4 version replacing
EPROM by ROM.
Two different commercial products are supported
by this device : ST7282A5 (no LCD driver) func-
tionnality described in specification SD70KL1618
ed. F) and ST7282B5 (LCD driver) functionnality
described in specification 96096 ed. B).
It contains an LCD controller/driver with 20 seg-
ment and 16 backplane outputs able to drive up to
20 x 16 = 320 segments.
The LCD control logic reads automatically data
from the LCD-RAM independently from the
ST7282 B5.
Further it contains up to 62 I/O pins, 24 of them
can be used as analog inputs to the 8 bit analog-
digital converter. Each digital I/O pin can individu-
ally be defined by software to work in one of the
following modes: open-drain output, push pull out-
put, input, input with pull-up (23 pins only) or inter-
rupt input with pull up (23 pins only). 3 of the digital
I/O pins serve as interface to the SIO. On pin PA4
the pull-up resistor is desactivated.
Port pins PD, PE, PF, PG and PH are multiplexed
with LCD Segment and backplane pins.
A 512 byte EEPROM for non volatile storage of
data is available. The programming voltage for
that device is generated on chip without external
components. So no extra supply is necessary. 16
bytes are protected against external readout.
One interrupt vector is connected to the I/O ports.
Five more interrupt vectors are available for the
timer, the ADC, the serial I/O interface and the
Group & Block Sync module (2). The watchdog
can be set by the user in 64 increments from
2.8msec to 182msec ( fOSC = 8.55 MHz ).
A synchronous 8 bit serial interface for serial data
IN/OUT is also implemented.
RDS signals can be decoded with the help of RDS
filter, RDS demodulator and Group & Block Sync
module.
1.2 Parameters
The values below substitute the corresponding values in the specifications of dedicated functions.
1.2.1 Absolute maximum ratings
Supply voltage
Input voltage*
Output voltage*
Input current
Output current*
Power dissipation
Storage temperature
Operation temperature
Display voltage
Output voltage Seg+COM
ESD
LU susceptibility
( VDD - VSS )
VIN
VOUT
Iin
IOUT
PD
Tstg
Tamb
(VLCD - VSS)
VOUT
ESD
LU
-0.3 ... +7V
VSS-0.3V...VDD+0.3V
VSS-0.3V ... VDD+0.3V
-10 ... +10mA
-10 ... + 10mA
tbd
-55 ... +125°C
-40 ... +85°C
VDD ... 7V
VSS-0.3V ... VLCD+0.3V
2500V
VDDA, Pin 52 - Class C
1.2.2 Recommended operating conditions
Supply voltage
Supply votage difference
(VDD - VSS)
(VDD, VDDP, VDDA)
(VSS, VSSP, VSSA)
4.5 ... 5.5V
50mV
The maximum accumulated current of all I/O pins
should not exceed 40 mA for VDDP and 40 mA for
VSSP.
* except LCD pins
** MIL 883B Mode, 100pF through 1.5k
Family
ST7
Issuer Ref.
PG-RO
Chrono
97115
7282A5B5
March 26, 1997
Previous Ref
Edition
Target C
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ST7282A5 - ST7282B5 - ROM FROM EPROM
1.2.3 Electrical Characteristics
The values given in the specifications of dedicated functions are generally not applicable for chips. There-
fore, only the limits listed below are valid for the product. T = -40 ... +85°C, VDD - VSS = 5V unless otherwise
specified.
PARAMETER
Supply voltage
Supply current Run Mode
SYMBOL
VDD
IDD
Supply current Wait Mode
IDD
Supply current slow wait mode
Supply current halt mode
Supply current Reset Mode
IDD
IDD
IDD
Display voltage
Supply voltage differences
(VDD, VDDP, VDDA)
(VSS, VSSP, VSSA)
OSCILLATOR:
Input/output cap Cin, Cout
Oscillation frequency 1)
Built up time 2)
VLCD
VD
fOSC
tBU
RESET:
Input current 3)
Input current 4)
Input current 5)
Input voltage high
Input voltage low
POWER-ON RESET
Supply rise time
Supply recovery time 6)
Trigger level on
Trigger level off
RDS FILTER:
Center frequency
3dB Bandwith
Gain
Attenuation
-IR
IR
IR
VR
VR
tr
trec
Vtlon
Vtloff
fc
BW
G
A
Input impedance
Load impedance
MPX input signal
RI
RL
VIN
Family Issuer Ref. Chrono
97115
ST7 PG-RO
7282A5B5
CONDITION
fOSC=8.55MHz
no output load
fOSC=8.55MHz
WD, Timer, LCD active
no output load
no output load
VRESET=VSS
f=8.55MHz
VDD = 4.5V
VDD=5.0V
C1=C2=22pF
Crystal
VR=VSS
VR=VDD
VR=VDD
10%-90%
Vin = 3mVRMS
57 KHz, Vin = 3mVRMS
f = ±4 KHz
f = 38 KHz
f = 67 KHz
March 26, 1997
MIN
4.5
-
-
-
-
-
VDD
-
TYP MAX
- 5.5
10 20
35
0.7 2
- 100
10 15
-7
- 50
UNIT
V
mA
mA
mA
µA
mA
V
mV
8.55
-
8.55
8
9.00
8.55
20
pF
MHz
ms
+50 +100
-
+10 +20
-
-1
-
--
0.7VDD - 0.2VDD
.01 - 10
10 -
-
1.4 .-
-
- -3
µA
µA
mA
V
V
ms
ms
V
V
56.5 57 57.5 KHz
2.5 3 3.5 KHz
18 20 22
dB
18 22
-
dB
50 80
-
dB
35 50
-
dB
100 160 200
K
1 - - M
170 250 600 mVRMS
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Edition
Target C
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