SSM25G45EM Datasheet PDF - Silicon Standard

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SSM25G45EM
Silicon Standard

Part Number SSM25G45EM
Description N-channel Insulated-Gate Bipolar Transistor
Page 4 Pages


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SSM25G45EM
N-CHANNEL INSULATED-GATE BIPOLAR TRANSISTOR
High input impedance
High peak current capability
4.5V gate drive
C
C
C
C
SO-8
G
E
E
E
Absolute Maximum Ratings
Symbol
Parameter
VCE Collector-Emitter Voltage
VGE Gate-Emitter Voltage
VGEP
Pulsed Gate-Emitter Voltage
ICP
PD @ TC=25°C1
Pulsed Collector Current
Maximum Power Dissipation
TSTG
Storage Temperature Range
TJ Operating Junction Temperature Range
VCE
ICP
G
Rating
450
±6
±8
150
2.5
-55 to 150
-55 to 150
450V
150A
C
E
Units
V
V
V
A
W
°C
°C
Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
IGES
Gate-Emitter Leakage Current
VGE=± 6V, VCE=0V
- - 10 µA
ICES
Collector-Emitter Leakage Current (Tj=25°C)
VCE=450V, VGE=0V
- - 10 µA
VCE(sat)
Collector-Emitter Saturation Voltage VGE=4.5V, ICP=150A (Pulsed)
- 68V
VGE(th)
Gate Threshold Voltage
VCE=VGE, IC=250uA
0.35 - 1.2 V
Qg Total Gate Charge
IC=50A
- 64.5 - nC
Qge Gate-Emitter Charge
VCE=360V
- 7 - nC
Qgc Gate-Collector Charge
VGE=5V
- 30 - nC
td(on)
Turn-on Delay Time
VCC=225V
- 11.5 -
ns
tr Rise Time
td(off)
Turn-off Delay Time
IC=50A
RG=25
- 24.5 -
- 150 -
ns
ns
tf Fall Time
VGE=5V
- 3.3 - µs
Cies Input Capacitance
VGE=0V
- 2227 - pF
Coes Output Capacitance
VCE=25V
- 200 - pF
Cres
RthJA1
Reverse Transfer Capacitance f=1.0MHz
Thermal Resistance Junction-Ambient
- 79 - pF
- - 50 °C/W
Notes:
1.Surface mounted on 1 in2 copper pad of FR4 board ; 125°C/W when mounted on min. copper pad.
9/21/2004 Rev.2.01
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180
160 T A =25 o C
140
5.0V
4.5V
4.0V
120
100 3.0V
80
60
2.0V
40
20 VG=1.0V
0
0 2 4 6 8 10
V CE , Collector-Emitter Voltage (V)
Fig 1. Typical Output Characteristics
SSM25G45EM
140
120 T A =150 o C
100
80
5.0V
4.5V
4.0V
3.0V
60
2.0V
40
20
VG=1.0V
0
0 2 4 6 8 10 12
V CE , Collector-Emitter Voltage (V)
Fig 2. Typical Output Characteristics
160
V CE =4.5V
120 25°C
70°C
125°C
T A =150°C
80
40
10
V GE =4.5V
8
6
4
2
I C =130A
I C =100A
I C =50A
0
012345
V GE , Cate-Emitter Voltage (V)
Fig 3. Collector Current vs.
Gate-Emitter Voltage
1.5
6
0
0 20 40 60 80 100 120 140 160
Junction Temperature ( o C)
Fig 4. Collector- Emitter Saturation Voltage
vs. Junction Temperature
200
1.2 160
0.9 120
0.6 80
0.3 40
0
-50 0 50 100
Junction Temperature ( o C )
Fig 5. Gate Threshold Voltage
vs. Junction Temperature
150
0
01234567
V GE , Gate-to-Emitter Voltage (V)
Fig 6. Minimum Gate Drive Area
9/21/2004 Rev.2.01
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10000
1000
100
f=1.0MHz
Cies
Coes
Cres
10
1 5 9 13 17 21 25 29
VCE, Collector-Emitter Voltage (V)
Fig 7. Typical Capacitance Characterisitics
SSM25G45EM
12
11
10 I CP =50A
V CC =360V
9
8
7
6
5
4
3
2
1
0
0 30 60 90 120
Q G , Gate Charge (nC)
150
Fig 8. Gate Charge Waveform
RG G
+
- 5V
RC
C VCE
TO THE
OSCILLOSCOPE
225 V
E
VGE
VCE
90%
10%
VGE
td(on) tr
td(off) tf
Fig 9. Switching Time Test Circuit
Fig 10. Switching Time Waveform
VCE
C
G
TO THE
OSCILLOSCOPE
300V
E VGE
+
- 1~3mA
IG IC
Flasher
RG
VG
VCM = 300V
CM =100uF
Vtrig
+
CM _ VCM
IGBT
ICP = 150A
VG =5V
Fig 11. Gate Charge Test Circuit
Fig 12. Application Test Circuit
9/21/2004 Rev.2.01
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SSM25G45EM
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
9/21/2004 Rev.2.01
www.SiliconStandard.com
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