SS1102C Datasheet PDF - ETC

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SS1102C
ETC

Part Number SS1102C
Description Integrated MCU with Spread-Spectrum Transceiver (SST)
Page 30 Pages


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9/12/98
SS1102C
Integrated MCU with Spread-Spectrum
Transceiver (SST)
External Specification
PRELIMINARY (V 1.8)
 
         
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Table of Contents
1. Description .........................................................................................................1
2. Features ..............................................................................................................1
3. SS1102C Block Diagram ...................................................................................2
4. Pin Description ..................................................................................................3
5. CPU ....................................................................................................................5
6. Memory organization .........................................................................................5
6.1. Data memory ..........................................................................................5
6.2. Program memory ...................................................................................6
7. Special function registers ...................................................................................7
7.1. Stack Pointer (SP) ..................................................................................8
7.2. Data Pointer (DPTR) ..............................................................................8
7.3. Program Status Word (PSW) .................................................................8
7.4. Accumulator (ACC) ...............................................................................9
7.5. B Register (B) ........................................................................................9
7.6. Memory Size Register (MSIZ) ..............................................................9
7.7. Interrupts ................................................................................................9
8. Time Base Timer ................................................................................................10
8.1. Overview ................................................................................................10
8.2. Time Base Timer Control Register (TBCR) ..........................................11
8.3. TB-Timer Counter Register (TBCNT) ..................................................13
8.4. TB-Timer Data Register (TBDAT) ........................................................14
9. Capture Timers 1/2 .............................................................................................15
9.1. Overview ................................................................................................15
9.2. Auto-Reload Mode ................................................................................16
9.3. Up Down-Count Mode ..........................................................................16
9.4. Capture Mode ........................................................................................17
9.5. Capture Timer Control Registers (CT1CR/CT2CR) .............................18
9.6. Capture Timer-1 Status Registers (CT1SR) ...........................................21
9.7. C-Timer Counter Registers ...................................................................22
9.8. C-Timer Data Register ..........................................................................23
10. WatchDog Timer ..............................................................................................25
10.1. Overview ..............................................................................................25
10.2. WatchDog Timer Control Register (WDCR) .......................................26
10.3. WatchDog Timer Register (WDCNT) .................................................28
10.4. Operation .............................................................................................29
11. SPI (Serial Peripheral Interface) ......................................................................30
11.1. Overview ..............................................................................................30
PRELIMINARY V1.8
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11.2. SPI Pin and Timing Description ....................................................30
11.3. SPI Timing Description ..................................................................30
11.4. SPI Operation .................................................................................31
11.5. SPI Control Register (SPICR) ........................................................33
11.6. SPI Status Register (SPI1SR) ........................................................34
11.7. SPI Shift Register (SPIDAT) ..........................................................35
12. Direct Sequence Spread Spectrum Baseband Modem (SSTM) .................37
12.1. Receiver .........................................................................................37
12.2. Transmitter .....................................................................................37
12.3. TDD Controller ..............................................................................38
12.4. FIFOs .............................................................................................38
12.5. Master Clock Generator .................................................................38
12.6. Full-Duplex Operation ...................................................................38
12.7. TDD Protocol .................................................................................39
12.8. System Delay .................................................................................41
12.9. Timing Information ........................................................................42
12.9.1 Full Duplex Operations .....................................................42
12.9.2 Threshold Value Calculation .............................................43
12.10. Half-duplex Operation .................................................................44
12.11. Reading the Signaling Word and S/N Data ..................................47
12.12. Control Registers .........................................................................48
12.13. SSTM Control Registers ..............................................................48
12.14. Configuration Information Bits ...................................................51
12.15. RF/IF Analog Interface ................................................................52
12.16. Programming the SSTM ..............................................................54
12.17. PN Sequence and UW Selection ..................................................55
12.18. PN Sequence Selection ................................................................55
12.19. UW Selection ...............................................................................56
12.20. Generating the PN and UW sequences ........................................57
13. Power-Saving Modes .................................................................................58
13.1. Overview ........................................................................................58
13.2. Mode Definition and Transition .....................................................59
13.3. FastAll mode (a Clocking Mode) ..................................................60
13.4. SlowAll mode (a Clocking Mode) .................................................60
13.5. StopAll mode (a Clocking Mode) ..................................................60
13.6. FastPeri mode (a Clocking Mode) .................................................61
13.7. SlowPeri mode (a Clocking Mode) ...............................................61
13.8. NorPin mode (a Pin State Mode) ...................................................61
13.9. HIZ mode (a Pin State Mode) ........................................................61
13.10. Power-Saving Control Register (PSCR) ......................................62
13.11. Stop Release Register (SREL) .....................................................64
ii PRELIMINARY V1.8



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14. Port Definitions ................................................................................................65
14.1. Overview ..............................................................................................65
14.2. Read-Modify-Write Feature .................................................................66
14.3. PCR (Port Control Register) ................................................................67
14.4. ZCR (Hi-Z Control Register) ...............................................................68
14.5. PAD Cell ..............................................................................................69
14.6. P0 (Port-0) ............................................................................................69
14.7. P2 (Port-2) ............................................................................................73
14.8. P1 (Port-1) ............................................................................................76
14.9. P3 (Port-3) ............................................................................................79
14.10. Port-4 .................................................................................................83
15. External Interrupts ...........................................................................................87
15.1. Overview ..............................................................................................87
15.2. Interrupt Control Block ........................................................................87
15.3. Interrupt Request Registers (INT0, INT1, INT2) ................................92
15.3.1 Interrupt Source Enable Registers (ISE0, ISE1, ISE2) ...........93
15.3.2 Interrupt Group Enable Register (IE) .....................................95
15.3.3 Interrupt Priority Register (IP) ................................................95
15.3.4 Interrupt Processing ................................................................96
16. SS1102C Special Modes ..................................................................................98
16.1. TEST ROM (Using Auxiliary RAM) ..................................................98
16.2. EMULATION MODE .........................................................................98
16.3. MULTICHIP PROGRAM MEMORY INTERFACE ..........................101
16.4. EXTERNAL MEMORY MODE .........................................................102
17. Comparator module .........................................................................................104
17.1. General Information .............................................................................104
17.2. Functional Description .........................................................................104
17.3. Block Diagram .....................................................................................105
17.4. Comparator Control Register ...............................................................105
17.5. Comparator I/O plot .............................................................................106
18. Power-On Reset (POR) ....................................................................................107
18.1. General .................................................................................................107
18.2. Operation .............................................................................................107
18.3. Crystal Oscillator Start-Up Time .........................................................107
19. Low Battery Detect (LBD) - Low Voltage Reset .............................................110
19.1. General Information .............................................................................110
19.2. Functional Description .........................................................................110
19.3. Low Battery Detect, Low Voltage Reset Control Register ..................111
19.4. TIMING DIAGRAMS .........................................................................113
20. DC PARAMETRICS .......................................................................................114
PRELIMINARY V1.8
iii



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