SP721 Datasheet PDF - LittelFuse

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SP721
LittelFuse

Part Number SP721
Description Electronic Protection Array for ESD snd Over Voltage Protection
Page 6 Pages


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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP721
The SP721 is an array of SCR/Diode bipolar structures for ESD and
over-voltage protection to sensitive input circuits. The SP721 has 2
protection SCR/Diode device structures per input. There are a total of
6 available inputs that can be used to protect up to 6 external signal or
bus lines. Over-voltage protection is from the IN (Pins 1 - 3 and Pins
5 - 7) to V+ or V-.
The SCR structures are designed for fast triggering at a threshold of one
+VBE diode threshold above V+ (Pin 8) or a -VBE diode threshold below
V- (Pin 4). From an IN input, a clamp to V+ is activated if a transient
pulse causes the input to be increased to a voltage level greater than
one VBE above V+. A similar clamp to V- is activated if a negative pulse,
one VBE less than V-, is applied to an IN input. Standard ESD Human
Body Model (HBM) Capability is:
HBM
STANDARD
MODE
IEC 61000-4-2 Air
Direct
Direct, Dual Pins
MIL-STD-3015.7 Direct, In-Circuit
R C ESD (V)
330150pF >15kV
330150pF >4kV
330150pF >8kV
1.5k100pF >15kV
Refer to Figure 1 and Table 1 for further detail. Refer to Application
Notes AN9304 and AN9612 for additional information.
Ordering Information
PART NO.
SP721AP
SP721AB
SP721ABT
TEMP. RANGE
(oC)
-40 to 105
-40 to 105
-40 to 105
PACKAGE
8 Ld PDIP
8 Ld SOIC
8 Ld SOIC
Tape and Reel
PKG.
NO.
E8.3
M8.15
M8.15
Min.
Order
2000
1960
2500
Pinout
SP721 (PDIP, SOIC)
TOP VIEW
IN 1
IN 2
IN 3
V- 4
8 V+
7 IN
6 IN
5 IN
Features
• ESD Interface Capability for HBM Standards
- MIL STD 3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15kV
- IEC 61000-4-2, Direct Discharge,
- Single Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (Level 2)
- Two Inputs in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . 8kV (Level 4)
- IEC 61000-4-2, Air Discharge . . . . . . . . . . . . . . . . . . 15kV (Level 4)
• High Peak Current Capability
- IEC 61000-4-5 (8/20µs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3A
- Single Pulse, 100µs Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . ±2A
- Single Pulse, 4µs Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . ±5A
• Designed to Provide Over-Voltage Protection
- Single-Ended Voltage Range to . . . . . . . . . . . . . . . . . . . . . . . . +30V
- Differential Voltage Range to. . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Fast Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2ns Rise Time
• Low Input Leakages . . . . . . . . . . . . . . . . . . . . . . . . 1nA at 25oC Typical
• Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3pF Typical
• An Array of 6 SCR/Diode Pairs
• Operating Temperature Range . . . . . . . . . . . . . . . . . . . . -40oC to 105oC
Applications
• Microprocessor/Logic Input Protection
• Data Bus Protection
• Analog Device Input Protection
• Voltage Clamp
Functional Block Diagram
V+ 8
IN 1
IN 2
3, 5-7
IN
V- 4
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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP721
Absolute Maximum Ratings
Thermal Information
Continuous Supply Voltage, (V+) - (V-). . . . . . . . . . . . . . . . . . . . . . . . . +35V
Forward Peak Current, IIN to VCC , IIN to GND
(Refer to Figure 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2A, 100µs
ESD Ratings and Capability (Figure 1, Table 1)
Load Dump and Reverse Battery (Note 2)
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Maximum Storage Temperature Range . . . . . . . . . . . . . . . . . . . . -65oC to 150oC
Maximum Junction Temperature (Plastic Package) . . . .. . . . . . . . . . . . . . . . 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . . .. . . . . . . . . . . .300oC
(SOIC Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications T A = -40oC to 105oC, VIN = 0.5VCC , Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Voltage Range,
VSUPPLY = [(V+) - (V-)]
Forward Voltage Drop
IN to V-
IN to V+
Input Leakage Current
Quiescent Supply Current
Equivalent SCR ON Threshold
VSUPPLY
VFWDL
VFWDH
IIN
IQUIESCENT
IIN = 1A (Peak Pulse)
Note 3
- 2 to 30 -
-2-
-2-
-20 5 +20
- 50 200
- 1.1 -
V
V
V
nA
nA
V
5
Equivalent SCR ON Resistance
VFWD/IFWD; Note 3
- 1 -
Input Capacitance
CIN
- 3 - pF
Input Switching Speed
tON
- 2 - ns
NOTES:
2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the
V+ and V- Pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should
be connected in series between the external supply and the SP721 supply pins to limit reverse battery current to within the rated maximum
limits. Bypass capacitors of typically 0.01µF or larger from the V+ and V- Pins to ground are recommended.
3. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance”. These characteristics are given here
for thumb-rule information to determine peak current and dissipation under EOS conditions.
ESD Capability
TABLE 1. ESD TEST CONDITIONS
ESD capability is dependent on the application and defined test standard.The
evaluation results for various test standards and methods based on Figure 1
are shown in Table 1.
For the “Modified” MIL-STD-3015.7 condition that is defined as an “in-circuit”
method of ESD testing, the V+ and V- pins have a return path to ground and
the SP721 ESD capability is typically greater than 15kV from 100pF through
1.5k. By strict definition of MIL-STD-3015.7 using “pin-to-pin” device testing,
the ESD voltage capability is greater than 6kV. The MIL-STD-3015.7 results
were determined from AT&T ESD Test Lab measurements.
The HBM capability to the IEC 61000-4-2 standard is greater than 15kV
for air discharge (Level 4) and greater than 4kV for direct discharge
(Level 2). Dual pin capability (2 adjacent pins in parallel) is well in excess
of 8kV (Level 4).
For ESD testing of the SP721 to EIAJ IC121 Machine Model (MM) standard,
the results are typically better than 1kV from 200pF with no series resistance.
STANDARD
TYPE/MODE
MIL-STD-3015.7 Modified HBM
R D CD ±VD
1.5k100pF 15kV
Standard HBM
1.5k100pF 6kV
IEC 61000-4-2 HBM, Air Discharge
330150pF 15kV
HBM, Direct Discharge 330150pF 4kV
HBM, Direct Discharge, 330150pF 8kV
Two Parallel Input Pins
EIAJ IC121
Machine Model
0k200pF 1kV
R1 RD
CHARGE
SWITCH
H.V.
SUPPLY
±VD
DISCHARGE
SWITCH
CD
IN
DUT
IEC 1000-4-2: R1 50 to 100M
MIL-STD-3015.7: R 11 to 10M
FIGURE 1. ELECTROSTATIC DISCHARGE TEST
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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP721
100 TA = 25oC
SINGLE PULSE
80
60
40
20
0
600
800 1000
FORWARD SCR VOLTAGE DROP (mV)
1200
FIGURE 2. LOW CURRENT SCR FORWARD VOLTAGE DROP
CURVE
+VCC
INPUT
DRIVERS
OR
SIGNAL
SOURCES
2.5 TA = 25oC
SINGLE PULSE
2
1.5
1
EQUIV. SAT. ON
THRESHOLD ~ 1.1V
0.5
IFWD
VFWD
0
0 12
FORWARD SCR VOLTAGE DROP (V)
3
FIGURE 3. HIGH CURRENT SCR FORWARDVOLTAGE DROP
CURVE
+VCC
LINEAR OR
DIGITAL IC
INTERFACE
IN 1 - 3
IN 5 - 7
TO +VCC
V+
SP721
V-
SP721 INPUT PROTECTION CIRCUIT (1 OF 6 SHOWN)
FIGURE 4. TYPICAL APPLICATION OF THE SP721 AS AN INPUT CLAMP FOR OVER-VOLTAGE, GREATER THAN 1VBE ABOVE V+ OR
LESS THAN -1V BE BELOW V-
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TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP721
Peak Transient Current Capability of the SP721
The peak transient current capability rises sharply as the width of the
current pulse narrows. Destructive testing was done to fully evaluate the
SP721’s ability to withstand a wide range of peak current pulses vs time.
The circuit used to generate current pulses is shown in Figure 5.
The test circuit of Figure 5 is shown with a positive pulse input. For a
negative pulse input, the (-) current pulse input goes to an SP721 ‘IN’
input pin and the (+) current pulse input goes to the SP721 V- pin. The
V+ to V- supply of the SP721 must be allowed to float. (i.e., It is not tied
to the ground reference of the current pulse generator.) Figure 6 shows
the point of overstress as defined by increased leakage in excess of the
data sheet published limits.
The maximum peak input current capability is dependent on the ambient
temperature, improving as the temperature is reduced. Peak current
curves are shown for ambient temperatures of 25oC and 105oC and a 15V
power supply condition. The safe operating range of the transient peak
current should be limited to no more than 75% of the measured over-
stress level for any given pulse width as shown in the curves of Figure 6.
Note that adjacent input pins of the SP721 may be paralleled to improve
current (and ESD) capability. The sustained peak current capability is
increased to nearly twice that of a single pin.
VARIABLETIME DURATION
+ R1 CURRENT PULSE GENERATOR
VX
-
CURRENT
SENSE
(-)
(+)
1 IN
V+ 8
VOLTAGE
PROBE
2 IN SP721 IN 7
3 IN
IN 6
4 V-
IN 5
+
C1
-
R1 ~ 10TYPICAL
VX ADJ. 10V/A TYPICAL
C1 ~ 100µF
FIGURE 5. TYPICAL SP721 PEAK CURRENT TEST CIRCUIT
WITH A VARIABLEPULSE WIDTH INPUT
7
CAUTION: SAFE OPERATING CONDITIONS LIMIT
6 THE MAXIMUM PEAK CURRENT FOR A GIVEN
PULSE WIDTH TO BE NO GREATER THAN 75%
OF THE VALUES SHOWN ON EACH CURVE.
5
TA = 25oC
V+ TO V- SUPPLY = 15V
4
3 TA = 105oC
2
1
0
0.001
0.01
0.1 1
PULSE WIDTH TIME (ms)
10
100 1000
FIGURE 6. SP721 TYPICAL SINGLE PULSE PEAK CURRENT CURVES SHOWING THE MEASURED POINT OF OVERSTRESS IN
AMPERES vs PULSE WIDTH TIME IN MILLISECONDS
5
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