SI8261 Datasheet PDF - Silicon Laboratories

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SI8261
Silicon Laboratories

Part Number SI8261
Description 4.0 A ISOLATED GATE DRIVERS
Page 30 Pages


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Si826x
5 KV LED EMULATOR INPUT, 4.0 A ISOLATED GATE DRIVERS
Features
Pin-compatible, drop-in upgrades for Robust protection features
popular high speed opto-coupled
Multiple UVLO ordering options
gate drivers
(5, 8, and 12 V) with hysteresis
Low power diode emulator simplifies 60 ns propagation delay,
design-in process
independent of input drive current
0.6 and 4.0 Amp peak output drive Wide VDD range: 5 to 30 V
current
3.75 and 5 kV reinforced isolation
Rail-to-rail output voltage
UL, CSA, VDE
Performance and reliability
AEC-Q100 qualified
advantages vs. opto-drivers
Wide operating temperature range
Resistant to temperature and age –40 to +125 °C
10x lower FIT rate for longer
service life
RoHS-compliant packages
14x tighter part-to-part matching
SOIC-8 (Narrow body)
DIP8 (Gull-wing)
Higher common-mode transient
SDIP6 (Stretched SO-6)
immunity: >50 kV/µs typical
LGA8
Applications
IGBT/ MOSFET gate drives
Industrial, HEV and renewable
energy inverters
AC, Brushless and DC motor
controls and drives
Variable speed motor control in
consumer white goods
Isolated switch mode and UPS
power supplies
Safety Regulatory Approvals (Pending)
UL 1577 recognized
VDE certification conformity
Up to 5000 Vrms for 1 minute
IEC60747-5-2/VDE0884 Part 10
CSA component notice 5A approval
(basic/reinforced insulation)
IEC 60950-1, 61010-1, 60601-1 CQC certification approval
(reinforced insulation)
GB4943.1
Description
The Si826x isolators are pin-compatible, drop-in upgrades for popular opto-
coupled gate drivers, such as 0.6 A ACPL-0302/3020, 2.5 A HCPL-3120/ACPL-
3130, HCNW3120/3130, and similar opto-drivers. The devices are ideal for driving
power MOSFETs and IGBTs used in a wide variety of inverter and motor control
applications. The Si826x isolated gate drivers utilize Silicon Laboratories'
proprietary silicon isolation technology, supporting up to 5.0 kVRMS withstand
voltage per UL1577. This technology enables higher-performance, reduced
variation with temperature and age, tighter part-to-part matching, and superior
common-mode rejection compared to opto-coupled gate drivers. While the input
circuit mimics the characteristics of an LED, less drive current is required,
resulting in higher efficiency. Propagation delay time is independent of input drive
current, resulting in consistently short propagation times, tighter unit-to-unit
variation, and greater input circuit design flexibility. As a result, the Si826x series
offers longer service life and dramatically higher reliability compared to opto-
coupled gate drivers.
Pin Assignments:
See page 24
1
ANODE 2
CATHODE 3
e
UVLO
8 VDD
7 VO
6 VO
NC 4
5 GND
SOIC-8, DIP8, LGA8
Industry Standard Pinout
ANODE 1
NC 2
e
CATHODE 3
6 VDD
UVLO
5 VO
4 GND
SDIP6
Industry Standard Pinout
Patent pending
Preliminary Rev. 0.9 4/13
Copyright © 2013 by Silicon Laboratories
Si826x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
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Si826x
Functional Block Diagram
Diode
Emulator
A1
IF
C1
XMIT
VDD
REC
Output Driver
OUT
GND
Diode Emulator Model and I-V Curve
Anode
Cathode
10
2.2 V
700
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
5 10 15 20 25 30
I[mA]
2 Preliminary Rev. 0.9
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TABLE OF CONTENTS
Si826x
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.1. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1. Input Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2. Output Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.5. Parametric Differences between Si826x and HCPL-0302 and HCPL-3120
Opto Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6. Pin Descriptions (SOIC-8, DIP8, LGA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7. Pin Descriptions (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11. Package Outline: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
12. Land Pattern: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13. Package Outline: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
14. Land Pattern: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
15. Package Outline: LGA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
16. Land Pattern: LGA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.1. Si826x Top Marking (Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
17.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.3. Si826x Top Marking (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
17.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
17.5. Si826x Top Marking (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
17.6. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
17.7. Si826x Top Marking (LGA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
17.8. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Preliminary Rev. 0.9
3
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Si826x
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
Input Current
Operating Temperature (Ambient)
Symbol
VDD
IF(ON)
TA
Min
Typ
Max
Unit
5 — 30 V
6 — 30 mA
–40 — 125 °C
Table 2. Electrical Characteristics 1
VDD = 15 V or 30 V, GND = 0 V, IF = 6 mA, TA = –40 to +125 °C; typical specs at 25 °C
Parameter
Symbol
Test Conditions
Min Typ Max Units
DC Parameters
Supply Voltage2
Supply Current (Output High)
Supply Current (Output Low)
Input Current Threshold
Input Current Hysteresis
Input Forward Voltage (OFF)
VDD
IDD
IDD
IF(TH)
IHYS
VF(OFF)
(VDD – GND)
IF = 10 mA
VDD = 15 V
VDD = 30 V
VF = –0.3 to +1.5 V
VDD = 15 V
VDD = 30 V
Measured at ANODE with
respect to CATHODE.
5 — 30 V
— 1.8 2.4 mA
— 2.0 2.7 mA
— 1.5 2.1 mA
— 1.7 2.4 mA
6 — — mA
— 0.34 — mA
—— 1V
Input Forward Voltage (ON)
VF(ON)
Measured at ANODE with
respect to CATHODE.
1.6 — 2.8 V
Input Capacitance
CI f = 100 kHz,
VF = 0 V,
— 15 — pF
VF = 2 V
— 15 —
Output Resistance High
(Source)3
Output Resistance Low (Sink)3
Si826xAxx devices
ROH
Si826xBxx devices (IOH = -1 A)
Si826xAxx devices
ROL
Si826xBxx devices (IOL = 2 A) —
15 —
2.6 5.1
5.0 —
0.8 2.0
Notes:
1. See "8.Ordering Guide" on page 25 for more information.
2. Minimum value of (VDD - GND) decoupling capacitor is 1 µF.
3. Both VO pins are required to be shorted together for 4.0 A compliance.
4. When performing this test, it is recommended that the DUT be soldered to avoid trace inductances, which may cause
over-stress conditions.
4 Preliminary Rev. 0.9
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