SI510 Datasheet PDF - Silicon Laboratories


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SI510
Silicon Laboratories

Part Number SI510
Description (SI510 / SI511) CRYSTAL OSCILLATOR
Page 30 Pages

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Si510/511
CRYSTAL OSCILLATOR (XO) 100 kHZ TO 250 MHZ
Features
Supports any frequency from
3.3, 2.5, or 1.8 V operation
100 kHz to 250 MHz
Differential (LVPECL, LVDS,
Low jitter operation
HCSL) or CMOS output options
2 to 4 week lead times
Optional integrated 1:2 CMOS
Total stability includes 10-year
fanout buffer
aging
Runt suppression on OE and
Comprehensive production test
power on
coverage includes crystal ESR and Industry standard 5 x 7, 3.2 x 5,
DLD
and 2.5 x 3.2 mm packages
On-chip LDO regulator for power Pb-free, RoHS compliant
supply noise filtering
–40 to 85 oC operation
Applications
SONET/SDH/OTN
Gigabit Ethernet
Fibre Channel/SAS/SATA
PCI Express
3G-SDI/HD-SDI/SDI
Telecom
Switches/routers
FPGA/ASIC clock generation
Description
The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology
to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO
where a different crystal is required for each output frequency, the Si510/511
uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to
generate any frequency across this range. This IC-based approach allows
the crystal resonator to provide enhanced reliability, improved mechanical
robustness, and excellent stability. In addition, this solution provides superior
supply noise rejection, simplifying low jitter clock generation in noisy
environments. Crystal ESR and DLD are individually production-tested to
guarantee performance and enhance reliability. The Si510/511 is factory-
configurable for a wide variety of user specifications, including frequency,
supply voltage, output format, output enable polarity, and stability. Specific
configurations are factory-programmed at time of shipment, eliminating long
lead times and non-recurring engineering charges associated with custom
frequency oscillators.
Functional Block Diagram
VDD
OE
Low Noise Regulator
Fixed
Frequency
Oscillator
Any-Frequency
0.1 to 250 MHz
DSPLL® Synthesis
CLK+
CLK–
GND
Si5602
2.5x3.2mm
5x7mm and 3.2x5mm
Ordering Information:
See page 14.
Pin Assignments:
See page 12.
OE 1
4 VDD
GND 2
3 CLK
Si510 (CMOS)
NC 1
OE 2
GND 3
6 VDD
5 CLK–
4 CLK+
Si510(LVDS/LVPECL/HCSL/
Dual CMOS)
OOEE 11
66 VVDDDD
NNCC 22
55 CCLLKK––
GGNNDD 33
44 CCLLKK++
Si511(LVDS/LVPECL/HCSL/
Dual CMOS)
Rev. 1.3 12/17
Copyright © 2017 by Silicon Laboratories
Si510/511



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Si510/511
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . . 11
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Si510/511 Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Package Outline Diagram: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. PCB Land Pattern: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
8. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
10. Package Outline Diagram: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11. PCB Land Pattern: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12. Package Outline Diagram: 3.2 x 5 mm, 6-Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
13. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
14. Package Outline Diagram: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
15. PCB Land Pattern: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
17. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2 Rev. 1.3



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Si510/511
1. Electrical Specifications
Table 1. Operating Specifications
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Supply Voltage
Supply Current
Symbol
Test Condition
Min
Typ
Max
Unit
VDD
3.3 V option
2.97
3.3
3.63
V
2.5 V option
2.25
2.5
2.75
V
1.8 V option
1.71
1.8
1.89
V
IDD
CMOS, 100 MHz,
21
26 mA
single-ended
OE "1" Setting
OE "0" Setting
OE Internal Pull-Up/Pull-
Down Resistor*
VIH
VIL
RI
LVDS
— 19 23 mA
(output enabled)
LVPECL
— 39 43 mA
(output enabled)
HCSL
— 41 44 mA
(output enabled)
Tristate
— — 18 mA
(output disabled)
See Note
See Note
0.80 x VDD
V
— — 0.20 x VDD V
— 45
— k
Operating Temperature
TA
–40 —
85 oC
*Note: Active high and active low polarity OE options available. Active high option includes an internal pull-up.
Active low option includes an internal pull-down. See ordering information on page 14.
Rev. 1.3
3



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Si510/511
Table 2. Output Clock Frequency Characteristics
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Nominal Frequency
Total Stability*
Symbol
FO
FO
Temperature Stability
Test Condition
CMOS, Dual CMOS
LVDS/LVPECL/HCSL
Frequency Stability Grade C
Frequency Stability Grade B
Frequency Stability Grade A
Frequency Stability Grade C
Frequency Stability Grade B
Min
0.1
0.1
–30
–50
–100
–20
–25
Typ
Max
Unit
— 212.5 MHz
— 250 MHz
— +30 ppm
— +50 ppm
+100
ppm
— +20 ppm
— +25 ppm
Startup Time
Disable Time
Enable Time
Frequency Stability Grade A –50 — +50 ppm
TSU Minimum VDD until output
— — 10 ms
frequency (FO) within specification
TD FO 10 MHz
——
5 µs
FO < 10 MHz
— — 40 µs
TE FO 10 MHz
— — 20 µs
FO < 10 MHz
— — 60 µs
*Note: Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and vibration
(not under operation), and 10 years aging at 40 oC.
4 Rev. 1.3




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