RTM363-210 Datasheet PDF - REALTEK

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RTM363-210
REALTEK

Part Number RTM363-210
Description SINGLE CHIP CLOCK GENERATOR
Page 23 Pages


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REALTEK SINGLE CHIP
CLOCK GENERATOR
RTM363-210
RTM363-210
1. General Description .................................................... 1
2. Features........................................................................ 1
3. Revision History .......................................................... 2
4. Block Diagram............................................................. 3
5. Pin Assignment ............................................................ 3
6. Pin Description ............................................................ 4
Type ......................................................................... 4
Frequency Table....................................................... 5
CPU ......................................................................... 5
SRC ......................................................................... 5
3V66/AGP ............................................................... 5
PCI........................................................................... 5
Phase Table .............................................................. 5
7. Register Description.................................................... 6
8. Functionality.............................................................. 10
8.1 Block Mode.......................................................... 10
8.2 Word Mode........................................................... 10
8.3 Power Down......................................................... 11
8.4 Group Skew.......................................................... 12
8.5 Host Swing Select ................................................ 12
9. Electrical Characteristics ......................................... 13
9.1 DC Specifications ................................................ 13
9.2 AC Specifications................................................. 14
9.2.1 CPU 0.7V ..................................................... 14
9.2.2 SRC 0.7V...................................................... 15
9.2.3 3V66/AGP .................................................... 16
9.2.4 PCI................................................................ 16
9.2.5 REF............................................................... 17
9.2.6 DOT 48MHz................................................. 17
9.2.7 USB 48MHz ................................................. 18
9.2.8 VCH 48MHz................................................. 18
10. Mechanical Dimensions .......................................... 19
11. Demo Board Circuit ................................................ 20
12. Quartz Crystal Requirements ................................ 21
12.1 Frequency and Oscillation Circuits .................... 21
12.2 Crystal Requirements ......................................... 22
12.3 Load Capacitance (CL) ....................................... 22
12.4 Reference Table.................................................. 23
1. General Description
RTM363-210 is a 48-pin package, single-chip frequency generator that meets INTEL® CK409 clock synthesizer/driver
specification. This chip provides a standard serial bus for programmable clock functions. Through this interface, spread
spectrum technology can be enabled to reduce EMI.
2. Features
l CPU frequency ratio supports up to 400MHz
l Power down feature.
l Programmable spread spectrum depth.
l Programmable spread spectrum model.
l Programmable driving strength.
l Programmable skew delay.
l Programmable PLL frequency.
l Programmable SRC/AGP/PCI fixed mode.
l Programmable loop filter.
l Programmable smooth-divider.
l Programmable current Iref.
l Programmable watchdog & smooth reset.
l DOS,WIN9x/WIN2000/WINNT/XP apps
*FS_0/ REF-2
*FS_1/ REF-1
REF-0
VDD_3.3_REF
X1
X2
GND_REF
**FS_2/ PCIF - 0
**FS_4/ PCIF - 1
PCIF - 2
VDD_3.3_PCI
GND_PCI
PCI - 0
PCI - 1
PCI - 2
PCI - 3
VDD_3.3_PCI
GND_PCI
PCI - 5
PCI - 6
**SEL24_48#/24_48M
**FS3/DOT 48Mhz
USB 48Mhz
GND_48
2003/10/16
Datasheet
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDD_3.3_CORE
47 GND_CORE
46 Iref
45 RESET#
44 GND_CPU
43 CPU-1
42 CPU-1 #
41 VDD_3.3_CPU
40 CPU-0
39 CPU-0 #
38 GND_SRC
37 SRC
36 SRC #
35 VDD_3.3_SRC
34 *Vtt_Power_Good /PD#
33 SDATA
32 SCLK
31 3V66-0
30 3V66-1
29 GND_3V66
28 VDD_3.3_3V66
27 3V66-2
26 3V66-3/VCH 48M
25 VDD_3.3_48
Rev.0.5
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3. Revision History
Rev. No.
0.5 l Initial release spec.
Description
RTM363-210
Date
Oct.16 2003
2003/10/16
Datasheet
2
Rev.0.5
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4. Block Diagram
Sdata
Sclk standard serial
bus
FS0..FS4
ROM
CPU stop#
PCI stop#
PD#
PWRGD#
Digital
control
XTAL
PLL2
PLL1
RTM363-210
Current
PAD
CPU0..2
CPU#0..2
SRC C/T
IREF
Divider
&
Muxer
Delay
&
Stop
Buffer
&
Strength
control
REF0..1
PCIF0..2
PCI0..5
3V660..4
VCH48
USB48
DOT48
5. Pin Assignment
*FS_0/ REF-2
*FS_1/ REF-1
REF-0
VDD_3.3_REF
X1
X2
GND_REF
**FS_2/ PCIF - 0
**FS_4/ PCIF - 1
PCIF - 2
VDD_3.3_PCI
GND_PCI
PCI - 0
PCI - 1
PCI - 2
PCI - 3
VDD_3.3_PCI
GND_PCI
PCI - 5
PCI - 6
**SEL24_48#/24_48M
**FS3/DOT 48Mhz
USB 48Mhz
GND_48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2003/10/16
Datasheet
48 VDD_3.3_CORE
47 GND_CORE
46 Iref
45 RESET#
44 GND_CPU
43 CPU-1
42 CPU-1 #
41 VDD_3.3_CPU
40 CPU-0
39 CPU-0 #
38 GND_SRC
37 SRC
36 SRC #
35 VDD_3.3_SRC
34 *Vtt_Power_Good /PD#
33 SDATA
32 SCLK
31 3V66-0
30 3V66-1
29 GND_3V66
28 VDD_3.3_3V66
27 3V66-2
26 3V66-3/VCH 48M
25 VDD_3.3_48
3 Rev.0.5
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6. Pin Description
RTM363-210
In order to reduce pin counts, and therefore package size and cost, some pins have multiple functions. In those cases, the
functions are separated with a /symbol. Refer to the Pin Assignmentdiagram for a graphical representation.
Pin Name
*FS_0 / REF-2 1
Pin No.
*FS_1 / REF-1 2
REF-0
X1
X2
3
5
6
**FS_2 /
PCIF-0
8
**FS_4 /
PCIF-1
9
PCIF-2
10
PCI [0:3], PCI[5:6] 13, 14, 15, 16, 19, 20
RESET#
45
**SEL24_48# /
24_48M
21
**FS_3/
DOT 48MHz
22
USB 48MHz
3V66_3 /
VCH 48M
3V66[0:2]
SDATA
SCLK
23
26
31, 30,27
33
32
Vtt_Power_Good/
PD#
34
SRC & SRC# 37,36
CPU & CPU# [0:1] 39,40,42,43
Iref 46
VDD
GND
GND_CORE
VDD_CORE
4, 11, 17, 25, 28, 35, 41
7, 12, 18, 24, 29, 38, 44
47
48
Type
Description
Frequency Selection 0: FS_0 latched input for frequency selection. This pin serves as the
I/O
power-on select strap to determine devices operating frequency as described in frequency
Table.
Reference Clock: 3.3V 14.318 MHz clock output.
Frequency Selection 1: FS_1 latched input for frequency selection. This pin serves as the
I/O
power-on select strap to determine devices operating frequency as described in frequency
Table.
Reference Clock: 3.3V 14.318 MHz clock output.
O Reference Clock: 3.3V 14.318 MHz clock output.
I
Crystal Input: This pin has dual functions. It can be used as an external 14.318MHz
crystal connection or as an external reference frequency input.
O
Crystal Output: An output connection for an external 14.318MHz crystal connection. If
using an external reference, this pin must be left unconnected.
Frequency Selection 2 : FS_2 latched input for frequency selection. This pin serves as
I/O
the power-on select strap to determine devices operating frequency as described in
frequency Table
PCIF Clock 0 : 3.3V 33 MHz free-running PCI clock outputs.
Frequency Selection 4 : FS_4 latched input for frequency selection. This pin serves as
I/O
the power-on select strap to determine devices operating frequency as described in
frequency Table
PCIF Clock 1 : 3.3V 33 MHz free-running PCI clock outputs.
O PCIF Clock 2: 3.3V 33 MHz PCI clock outputs.
O PCI Clock 0 through 5: 3.3V 33 MHz PCI clock outputs.
O RESET# open drain output: Watchdog & smooth reset output.
I **SEL24_48#: Latched input for frequency selection.
O 24/48# MHz Clock Output: 3.3V fixed 24/48# MHz, non-spread spectrum clock output.
Frequency Selection 3: FS_3 latched input for frequency selection. This pin serves as the
I/O
power-on select strap to determine devices operating frequency as described in frequency
Table.
48 MHz Clock Output: 3.3V fixed 48 MHz, non-spread spectrum clock output.
O 48 MHz Clock Output: 3.3V fixed 48 MHz, non-spread spectrum clock output.
O
66 MHz Clock Output / 48Mhz Clock Output: 3.3V output clocks. The operating
frequency is controlled by registers.
O 66 MHz Clock Output: 3.3V 66MHz output clocks.
I/O Data pin for serial interface.
I Clock input pin for serial interface.
I
Vtt Power Good: LVTTL compatible input that is a level sensitive strobe used to
determine when FS[0:4] inputs are valid and OK to be sampled. One-shot function.
I
Power Down Control: LVTTL compatible input that places the device in power down
mode when held low.
O/C
Serial Reference Clock: Serial-ATA reference clock as current-mode differential pair
output. Output frequencies depending on the configuration of FS[0:4].
O/C
CPU Clock Outputs: Current-mode differential outputs. Output frequencies depending
on the configuration of FS[0:4].
I
Iref: A precision resistor is attached to this pin which is connected to the internal current
reference .
P
3.3V Power Connection: Power supply for REF output buffers, PCI output buffers, 48M
output buffers ,3V66MHz output buffers ,and CPU output buffers . Connect to 3.3V.
G Ground Connections: Connect all ground pins to the common system ground plane.
G
Ground Connections: Ground for internal core logical circuit . Connect all ground pins
to the common system ground plane.
P 3.3V Core Power : Power supply for internal core logical circuit . Connect to 3.3V.
Note: Internal 150K pull-up or pull-down resistors that is presented on input pins are marked with (*) and (**) respectively. Design should not rely solely on
internal pull-up or pull-down resistors to set I/O pins high or low respectively.
( * ):a input pin with internal 150K ohm pull-up resistor.
(**):a input pin with internal 150K ohm pull-down resistor.
2003/10/16
Datasheet
4
Rev.0.5
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