R5F5111JADFL Datasheet PDF - Renesas



Part Number R5F5111JADFL
Description 32 MHz 32-bit RX MCUs
Page 30 Pages

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RX111 Group
Renesas MCUs
32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory,
Jun 19, 2013
USB 2.0 full-speed host/function/OTG, up to 6 comms channels,
12-bit A/D, 8-bit D/A, RTC
32-bit RX CPU core
32 MHz maximum operating frequency
Capable of 50 DMIPS when operating at 32 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32-bit × 32-bit operations
Multiplication and division unit handles 32-bit × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
CISC Harvard architecture with five-stage pipeline
Variable-length instruction format, ultra-compact code
On-chip debugging circuit
Low power consumption functions
Operation from a single 1.8 to 3.6 V supply
Three low power consumption modes
On-chip flash memory for code, no wait states
Operation at 32 MHz, read cycle of 31.25 ns
No wait states for reading at full CPU speed
16 to 128 Kbyte capacities
Programmable at 1.8 V
For instructions and operands
On-chip data flash memory
8 Kbytes
1,000,000 Erase/Write cycles (typ.)
BGO (Background Operation)
On-chip SRAM, no wait states
8 to 16 Kbyte capacities
Data transfer controller (DTC)
Four transfer modes
Transfer can be set for each interrupt source.
Event link controller (ELC)
Module operation can be initiated by event signals
without going through interrupts.
Link operation between modules is possible while the
CPU is sleeping.
Reset and power supply voltage management
Six types including Power-On Reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External clock input frequency: Up to 20 MHz
Main clock oscillator frequency: 1 to 20 MHz
Sub-clock oscillator frequency: 32.768 kHz
PLL circuit input: 4 to 8 MHz
Low-speed on-chip oscillator: 4 MHz
High-speed on-chip oscillator: 32 MHz
IWDT-dedicated on-chip oscillator: 15 kHz
Generate a dedicated 32.768-kHz clock for the RTC
On-chip clock frequency accuracy measurement circuit
Realtime clock (RTC)
30-second, leap year, and error adjustment functions
Calendar count mode or binary count mode selectable
Capable of initiating exit from software standby mode
R01DS0190EJ0100 Rev.1.00
Jun 19, 2013
PLQP0064KB-A 10 × 10 mm, 0.5 mm pitch
PLQP0064GA-A 14 × 14 mm, 0.8 mm pitch
PLQP0048KB-A 7 × 7 mm, 0.5 mm pitch
PWQN0048KB-A 7 × 7 mm, 0.50 mm pitch
PWQN0040KC-A 6 × 6 mm, 0.50 mm pitch
PWLG0064KA-A 5 × 5 mm, 0.5 mm pitch
PWLG0036KA-A 4 × 4 mm, 0.5 mm pitch
Independent watchdog timer (IWDT)
15-kHz on-chip oscillator produces a dedicated clock
signal to drive IWDT operation.
On-chip functions for IEC 60730 compliance
Clock frequency accuracy measurement circuit, IWDT,
functions to assist in RAM testing, etc.
Up to six channels for communication
USB: USB 2.0 host (32 Kbyte or more ROM)/function/
On-The-Go (OTG) (one channel), full-speed = 12 Mbps,
low-speed = 1.5 Mbps, isochronous transfer, and BC
(Battery Charger) supported
SCI: Asynchronous mode, clock synchronous mode,
smart card interface (up to three channels)
I2C bus interface: Transfer at up to 400 kbps, capable of
SMBus operation (one channel)
RSPI (one channel)
Up to 8 extended-function timers
16-bit MTU: Input capture/output compare,
complementary PWM output, phase counting mode
(six channels)
16-bit CMT (two channels)
12-bit A/D converter
Up to 14 channels
1.0 μs minimum conversion speed
Double trigger (data duplication) function for motor
8-bit D/A converter
Two channels (for 64 pins only)
Temperature sensor
General I/O ports
5-V tolerant, open drain, input pull-up
Multi-function pin controller (MPC)
Multiple I/O pins can be selected for peripheral functions.
Operating temperature range
 40 to 85C
 40 to 105°C
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RX111 Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different
Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will
differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different
Table 1.1
Outline of Specifications (1/3)
Classification Module/Function
Maximum operating frequency: 32 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per clock cycle
Address space: 4-Gbyte linear
Register set
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32-bit × 32-bit 64-bit
On-chip divider: 32-bit ÷ 32-bit 32 bits
Barrel shifter: 32 bits
Capacity: 16 K /32 K /64 K /96 K /128 Kbytes
32 MHz, no-wait memory access
Programming/erasing method:
Serial programming (asynchronous serial communication/USB communication), self-programming
Capacity: 8 K /10 K /16 Kbytes
32 MHz, no-wait memory access
E2 DataFlash
Capacity: 8 Kbytes
Number of erase/write cycles: 1,000,000 (typ)
MCU operating mode
Single-chip mode
Clock generation circuit
Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator
Oscillation stop detection: Available
Clock frequency accuracy measurement circuit (CAC)
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the PCLK: 32 MHz (at max.)
The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)
The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16, 32,
RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
Voltage detection Voltage detection circuit
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
Low power
Low power consumption
Module stop function
Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
Function for lower operating Operating power control modes
power consumption
High-speed operating mode, middle-speed operating mode, and low-speed operating mode
Interrupt controller (ICUb)
Interrupt vectors: 82
External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
Non-maskable interrupts: 4 (NMI pin, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt,
and IWDT interrupt)
16 levels specifiable for the order of priority
R01DS0190EJ0100 Rev.1.00
Jun 19, 2013
Page 2 of 107
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RX111 Group
1. Overview
Table 1.1
Outline of Specifications (2/3)
Data transfer controller
I/O ports
General I/O ports
Event link controller (ELC)
Multi-function pin controller (MPC)
Multi-function timer pulse
unit 2 (MTU2a)
Port output enable 2
Compare match timer
Independent watchdog
timer (IWDTa)
Realtime clock (RTCA)
Serial communications
interfaces (SCIe, SCIf)
I2C bus interface (RIIC)
Serial peripheral interface
Transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Interrupts
Chain transfer function
64-pin /48-pin /40-pin /36-pin
I/O: 46/30/24/20
Input: 2/2/1/1
Pull-up resistors: 38/24/19/16
Open-drain outputs: 34/24/19/16
5-V tolerance: 4/4/4/4
Event signals of 35 types can be directly connected to the module
Operations of timer modules are selectable at event input
Capable of event link operation for port B
Capable of selecting the input/output function from multiple pins
(16 bits × 6 channels) × 1 unit
Time bases for the six 16-bit timer channels can be provided via up to 16 pulse-input/output lines and
three pulse-input lines
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
Input capture function
21 output compare/input capture registers
Pulse output mode
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Capable of generating conversion start triggers for the A/D converter
Controls the high-impedance state of the MTU’s waveform output pins
(16 bits × 2 channels) × 1 unit
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
14 bits × 1 channel
Count clock: Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
Clock source: Sub-clock
Calendar count mode or binary count mode selectable
Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt
3 channels (channel 1, 5: SCIe, channel 12: SCIf)
Serial communications modes: Asynchronous, clock synchronous, and smart card interface
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from MTU2 timers
Simple I2C
Simple SPI
Master/slave mode supported (SCIf only)
Start frame and information frame are included (SCIf only)
Start-bit detection in asynchronous mode: Low level or falling edge is selectable
1 channel
Communications formats:
I2C bus format/SMBus format
Master mode or slave mode selectable
Supports fast mode
1 channel
Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI
clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-
synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Choice of LSB-first or MSB-first transfer
The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or
32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
Double buffers for both transmission and reception
R01DS0190EJ0100 Rev.1.00
Jun 19, 2013
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RX111 Group
1. Overview
Table 1.1
Outline of Specifications (3/3)
USB 2.0 host/function
module (USBc)
12-bit A/D converter (S12ADb)
Temperature sensor (TEMPSa)
D/A converter (DA)
CRC calculator (CRC)
Data operation circuit (DOC)
Power supply voltages/Operating frequencies
Supply current
Operating temperature range
On-chip debugging system
USB Device Controller (UDC) and transceiver for USB 2.0 are incorporated.
Host (32-Kbyte or more ROM)/function module: 1 port
Compliant with USB version 2.0
Transfer speed: Full-speed (12 Mbps), low-speed (1.5 Mbps)
OTG (ON-The-Go) is supported.
Isochronous transfer is supported.
BC (Battery Charger) is supported.
1 unit (1 unit × 14 channels)
12-bit resolution
Minimum conversion time: 1.0 µs per channel when the ADCLK is operating at 32 MHz
Operating modes
Scan mode (single scan mode, continuous scan mode, and group scan mode)
Double trigger mode (duplication of A/D conversion data)
A/D conversion start conditions
A software trigger, a trigger from a timer (MTU), an external trigger signal, or ELC
1 channel
The voltage of the temperature is converted into a digital value by the 12-bit A/D converter.
2 channels
8-bit resolution
Output voltage: 0 V to VCC
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1
Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.
Comparison, addition, and subtraction of 16-bit data
VCC = 1.8 to 2.4 V: 8 MHz, VCC = 2.4 to 2.7 V: 16 MHz, VCC = 2.7 to 3.6 V: 32 MHz
3.2 mA at 32 MHz (typ.)
D version: 40 to +85°C, G version: 40 to +105°C
64-pin LFQFP (PLQP0064KB-A) 10 × 10 mm, 0.5 mm pitch
64-pin LQFP (PLQP0064GA-A) 14 × 14 mm, 0.8 mm pitch
64-pin WFLGA (PWLG0064KA-A) 5 × 5 mm, 0.5 mm pitch
48-pin LFQFP (PLQP0048KB-A) 7 × 7 mm, 0.5 mm pitch
48-pin HWQFN (PWQN0048KB-A) 7 × 7 mm, 0.5 mm pitch
40-pin HWQFN (PWQN0040KC-A) 6 × 6mm, 0.50mm pitch
36-pin WFLGA (PWLG0036KA-A) 4 × 4 mm, 0.5 mm pitch
E1 emulator (FINE interface)
R01DS0190EJ0100 Rev.1.00
Jun 19, 2013
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