QT60xx0 devices are digital burst mode charge-transfer (QT)
sensors designed specifically for matrix layout touch controls;
they include all signal processing functions necessary to
provide stable sensing under a wide variety of changing
conditions. Only a few external parts are required for
operation. The entire circuit can be built within a few square
centimeters of single-sided PCB area. CEM-1 and FR1
punched, single-sided materials can be used for the lowest
possible cost. The PCB’s rear can be mounted flush on the
back of a glass or plastic panel using a conventional
adhesive, such as 3M VHB two-sided adhesive acrylic film.
1.3 Enabling / Disabling Keys
The NDIL parameter is used to enable and disable keys in the
matrix. Setting NDIL = 0 for a key disables it (Section 6.5). At
no time can the number of enabled keys exceed the
maximum specified for the device (see Section 1.2).
On the QT60160, only the first 2 Y lines (Y0, Y1) are
operational by default. On the QT60160, to use keys located
on line Y2, one or more of the pre-enabled keys must be
disabled simultaneously while enabling the desired new keys.
This can be done in one Setups block load operation.
2 Hardware and Functional
Figure 1.1 Field Flow Between X and Y Elements
QT60xx0 devices employ transverse charge-transfer ('QT')
sensing, a technology that senses changes in electrical
charge forced across two electrode elements by a pulse edge
(Figure 1.1). QT60xx0 devices allow a wide range of key sizes
and shapes to be mixed together in a single touch panel.
The devices use an I2C interface to allow key data to be
extracted and to permit individual key parameter setup. The
command structure is designed to minimize the amount of
data traffic while maximizing the amount of information
In addition to normal operating and setup functions the device
can also report back actual signal strengths .
QmBtn™ software for the PC can be used to program the
operation of the IC, as well as read back key status and
signal levels in real time.
2.1 Matrix Scan Sequence
The circuit operates by scanning each key sequentially, key
by key. Key scanning begins with location X=0 / Y=0 (key 0).
X axis keys are known as rows while Y axis keys are referred
to as columns although this has no reflection on actual wiring .
Keys are scanned sequentially by row, for example the
sequence X0Y0 X1Y0 .... X7Y0, X0Y1, X1Y1... etc. Keys are
also numbered from 0...23. Key 0 is located at X0Y0.
Table 2.1 shows the key numbering.
Table 2.1 Key Numbers
X7 X6 X5 X4 X3 X2 X1 X0
Y0 7 6 5 4 3 2 1 0
Y1 15 14 13 12 11 10 9 8
Y2 23 22 21 20 19 18 17 16
Each key is sampled in a burst of acquisition pulses whose
length is determined by the Setups parameter BL (page 19);
this can be set on a per-key basis. A burst is completed
entirely before the next key is sampled; at the end of each
burst the resulting signal is converted to digital form and
processed. The burst length directly impacts key gain; each
key can have a unique burst length in order to allow tailoring
of key sensitivity on a key-by-key basis.
2.2 Burst Paring
Keys that are disabled by setting NDIL = 0 (Section 6.5,
page 18) have their bursts removed from the scan sequence
to save scan time. As a consequence, the fewer keys that are
used the faster the device can respond. All calibration times
are reduced when keys are disabled.
1.2 Part Differences
There are two versions of the device; one is capable of a
maximum of 16 keys (QT60160), the other is capable of a
maximum of 24 keys (QT60240).
These devices are identical in all respects, except for the
maximum number of keys specified. The keys can be located
anywhere within an electrical grid of 8 X and 3 Y scan lines.
Unused keys are always pared from the burst sequence in
order to optimize speed. Similarly, in a given part a lesser
number of enabled keys will cause any unused acquisition
burst timeslots to be pared from the sampling sequence to
optimize acquire speed. Thus, if only 14 keys are actually
enabled, only 14 timeslots are used for scanning.
2.3 Cs Sample Capacitor Operation
Cs capacitors absorb charge from the key electrodes on the
rising edge of each X pulse. On each falling edge of X, the Y
matrix line is clamped to ground to allow the electrode and
wiring charges to neutralize in preparation for the next pulse.
With each X pulse charge accumulates on Cs causing a
staircase increase in its differential voltage.
After the burst completes, the device clamps the Y line to
ground causing the opposite terminal to go negative. The
charge on Cs is then measured using an external resistor to
ramp the negative terminal upwards until a zero crossing is
achieved. The time required to zero cross becomes the
3 QT60240-ISG R8.06/0906