PCA9617A Datasheet PDF - NXP Semiconductors

www.Datasheet-PDF.com

PCA9617A
NXP Semiconductors

Part Number PCA9617A
Description Level translating Fm I2C-bus repeater
Page 24 Pages


PCA9617A datasheet pdf
Download PDF
PCA9617A pdf
View PDF for Mobile

No Preview Available !

PCA9617A
Level translating Fm+ I2C-bus repeater
Rev. 1 — 20 March 2013
Product data sheet
1. General description
The PCA9617A is a CMOS integrated circuit that provides level shifting between low
voltage (0.8 V to 5.5 V) and higher voltage (2.2 V to 5.5 V) Fast-mode Plus (Fm+) I2C-bus
or SMBus applications. While retaining all the operating modes and features of the
I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing
bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two
buses of 540 pF at 1 MHz or up to 4000 pF at lower speeds. Using the PCA9617A
enables the system designer to isolate two halves of a bus for both voltage and
capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance
when the PCA9617A is unpowered.
The 2.2 V to 5.5 V bus port B drivers have the static level offset, while the adjustable
voltage bus port A drivers eliminate the static offset voltage. This results in a LOW on the
port B translating into a nearly 0 V LOW on the port A which accommodates the smaller
voltage swings of lower voltage logic.
The static offset design of the port B PCA9617A I/O drivers prevents them from being
connected to the static or incremented offset of other bus buffers. Port A of two or more
PCA9617As can be connected together, however, to allow a star topography with port A
on the common bus, and port A can be connected directly to any other buffer with static or
incremented offset outputs. Multiple PCA9617As can be connected in series, port A to
port B, with no build-up in offset voltage with only time of flight delays to consider.
The PCA9617A drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above
2.2 V. The EN pin is referenced to VCC(B) and can also be used to turn the drivers on and
off under system control. Caution should be observed to only change the state of the
enable pin when the bus is idle.
The output pull-down on the port B internal buffer LOW is set for approximately 0.55 V,
while the input threshold of the internal buffer is set about 90 mV lower (0.45 V). When the
port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a latching condition from occurring. The output pull-down on port A drives a
hard LOW and the input level is set at 0.35VCC(A) to accommodate the need for a lower
LOW level in systems where the low voltage side supply voltage is as low as 0.8 V.
2. Features and benefits
2 channel, bidirectional buffer isolates capacitance and allows 540 pF on either side of
the device at 1 MHz and up to 4000 pF at lower speeds
Voltage level translation from 0.8 V to 5.5 V and from 2.2 V to 5.5 V
Footprint and functional replacement for PCA9517A at Fast-mode speeds
Port A operating supply voltage range of 0.8 V to 5.5 V with normal levels
Free Datasheet http://www.datasheet4u.com/



No Preview Available !

NXP Semiconductors
PCA9617A
Level translating Fm+ I2C-bus repeater
Port B operating supply voltage range of 2.2 V to 5.5 V with static offset level
5 V tolerant I2C-bus and enable pins
0 Hz to 1000 kHz clock frequency (the maximum system operating frequency may be
less than 1000 kHz because of the delays added by the repeater)
Active HIGH repeater enable input referenced to VCC(B)
Open-drain input/outputs
Latching free operation
Supports arbitration and clock stretching across the repeater
Accommodates Standard-mode, Fast-mode and Fast-mode Plus I2C-bus devices,
SMBus (standard and high power mode), PMBus and multiple masters
Powered-off high-impedance I2C-bus pins
ESD protection exceeds 5500 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: TSSOP8 and HWSON8
3. Ordering information
Table 1. Ordering information
Tamb = 40 C to +85 C.
Type number Topside
mark
Package
Name
PCA9617ADP P617A
TSSOP8[1]
PCA9617ATP P7A
HWSON8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm
plastic thermal enhanced very very thin small outline package;
no leads; 8 terminals; body 2 3 0.8 mm
Version
SOT505-1
SOT1069-2
[1] Also known as MSOP8.
3.1 Ordering options
Table 2. Ordering options
Type number Orderable
part number
Package Packing method
PCA9617ADP PCA9617ADPJ
PCA9617ATP PCA9617ATPZ
TSSOP8
HWSON8
Reel 13” Q1/T1
*standard mark SMD
Reel 7” Q2/T3 *standard mark
Minimum
order
quantity
2500
Temperature range
Tamb = 40 C to +85 C
4000
Tamb = 40 C to +85 C
PCA9617A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 March 2013
© NXP B.V. 2013. All rights reserved.
2 of 23
Free Datasheet http://www.datasheet4u.com/



No Preview Available !

NXP Semiconductors
4. Functional diagram
PCA9617A
Level translating Fm+ I2C-bus repeater
SDAA
PCA9617A
VCC(A)
VCC(B)
SDAB
SCLA
EN
VCC(B)
pull-up
resistor
GND
Fig 1. Functional diagram of PCA9617A
SCLB
002aag641
PCA9617A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 March 2013
© NXP B.V. 2013. All rights reserved.
3 of 23
Free Datasheet http://www.datasheet4u.com/



No Preview Available !

NXP Semiconductors
PCA9617A
Level translating Fm+ I2C-bus repeater
5. Pinning information
5.1 Pinning
VCC(A) 1
SCLA 2
SDAA 3
GND 4
PCA9617ADP
8 VCC(B)
7 SCLB
6 SDAB
5 EN
002aag643
Fig 2. Pin configuration for TSSOP8
(MSOP8)
terminal 1
index area
SDAA 1
GND 2
EN 3
SDAB 4
PCA9617ATP
8 SCLA
7 VCC(A)
6 VCC(B)
5 SCLB
002aag644
Transparent top view
Fig 3. Pin configuration for HWSON8
5.2 Pin description
Table 3.
Symbol
VCC(A)
SCLA
SDAA
GND
EN
SDAB
SCLB
VCC(B)
Pin description
Pin
TSSOP8
1
2
3
4
5
6
7
8
HWSON8
7
8
1
2[1]
3
4
5
6
Description
port A supply voltage (0.8 V to 5.5 V)
serial clock port A bus
serial data port A bus
supply ground (0 V)
active HIGH repeater enable input
serial data port B bus
serial clock port B bus
port B supply voltage (2.2 V to 5.5 V)
[1] HWSON8 package die supply ground is connected to both GND pin and exposed center pad. GND pin
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper head conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
PCA9617A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 March 2013
© NXP B.V. 2013. All rights reserved.
4 of 23
Free Datasheet http://www.datasheet4u.com/



PCA9617A datasheet pdf
Download PDF
PCA9617A pdf
View PDF for Mobile


Related : Start with PCA9617 Part Numbers by
PCA9617A Level translating Fm I2C-bus repeater PCA9617A
NXP Semiconductors
PCA9617A pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact