P3P4GF4BLF Datasheet PDF - Deutron Electronics

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P3P4GF4BLF
Deutron Electronics

Part Number P3P4GF4BLF
Description 4G Bits Die DDRIII SDRAM
Page 30 Pages


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4G B Die DDRIII SDRAM Specification
P3P4GF4BLF
Deutron Electronics Corp.
8F, 68, Sec. 3, NanKing E. RD., Taipei 104,
Taiwan, R.O.C.
TEL: (886)-2-2517-7768
FAX: (886)-2-2517-4575



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P3P4GF4BLF (256M words x 16 bits)
Specifications
Density: 4G bits
Organization
32M words 16 bits 8 banks
Package
96-ball FBGA
Lead-free (RoHS compliant) and Halogen-free
Power supply: VDD, VDDQ 1.5V 0.075V
Data rate
1600Mbps/1333Mbps/1066Mbps (max.)
2KB page size
Row address: A0 to A14
Column address: A0 to A9
Eight internal banks for concurrent operation
Interface: SSTL_15
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
Burst type (BT):
Sequential (8, 4 with BC)
Interleave (8, 4 with BC)
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
/CAS Write Latency (CWL): 5, 6, 7, 8
Precharge: auto precharge option for each burst
access
Driver strength: RZQ/7, RZQ/6 (RZQ = 240)
Refresh: auto-refresh, self-refresh
Refresh cycles
Average refresh period
7.8s at 0C TC  85C
3.9s at 85C TC  95C
Operating case temperature range
TC = 0C to +95C
Features
Double-data-rate architecture: two data transfers per
clock cycle
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
Multi Purpose Register (MPR) for pre-defined pattern
read out
ZQ calibration for DQ drive and ODT
Programmable Partial Array Self-Refresh (PASR)
/RESET pin for Power-up sequence and reset
function
SRT range:
Normal/extended
Programmable Output driver impedance control
Document No. E1801E22 (Ver. 2.2)



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MIRA 4G Bits DDR3 SDRAM
Data Sheet E1801E22 (Ver. 2.2)
2



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MIRA 4G Bits DDR3 SDRAM
Pin Configurations
/xxx indicates active low signal.
96-ball FBGA
1 23
78 9
A
VDDQ DQU5 DQU7
B
VSSQ VDD VSS
C
VDDQ DQU3 DQU1
D
VSSQ VDDQ DMU
E
VSS VSSQ DQL0
F
VDDQ DQL2 DQSL
G
VSSQ DQL6 /DQSL
H
VREFDQ VDDQ DQL4
J
NC VSS /RAS
K
ODT VDD /CAS
L
NC /CS /WE
M
VSS BA0 BA2
N
VDD A3
A0
P
VSS A5
A2
R
VDD A7
A9
T
VSS /RESET A13
DQU4 VDDQ VSS
/DQSU DQU6 VSSQ
DQSU DQU2 VDDQ
DQU0 VSSQ VDD
DML VSSQ VDDQ
DQL1 DQL3 VSSQ
VDD VSS VSSQ
DQL7 DQL5 VDDQ
CK VSS NC
/CK VDD CKE
A10(AP) ZQ NC
NC VREFCA VSS
A12(/BC) BA1 VDD
A1 A4 VSS
A11 A6 VDD
A14 A8 VSS
(Top view)
Pin name
Function
Pin name
Function
A0 to A14*2
BA0 to BA2*2
DQU0 to DQU7
DQL0 to DQL7
DQSU, /DQSU
DQSL, /DQSL
/CS*2
/RAS, /CAS, /WE*2
CKE*2
Address inputs
A10(AP): Auto precharge
A12(/BC): Burst chop
Bank select
Data input/output
Differential data strobe
Chip select
Command input
Clock enable
/RESET*2
VDD
VSS
VDDQ
VSSQ
VREFDQ
VREFCA
Active low asynchronous reset
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Reference voltage for DQ
Reference voltage
CK, /CK
DMU, DML
ODT*2
Differential clock input
Write data mask
ODT control
ZQ
NC*1
Reference pin for ZQ calibration
No connection
Notes: 1. Not internally connected with die.
2. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1801E22 (Ver. 2.2)
3



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