OPAMP1EVB Datasheet PDF - ON Semiconductor

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OPAMP1EVB
ON Semiconductor

Part Number OPAMP1EVB
Description Op Amp Evaluation Board Manual
Page 8 Pages


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OPAMP1EVB
Op Amp Evaluation
Board Manual
SOT23, SC70, and
SOIC8 Package
http://onsemi.com
Description
This document describes the SOT23, SC70, and SOIC8
package Op Amp evaluation board. It should be used in
conjunction with the appropriate data sheet which contains
full technical details on the device specification and
operation. This evaluation board is offered as a convenience
for the customers interested in performing their own
engineering characterization and performance assessment.
The evaluation board provides a 50 W controlled impedance
environment. The evaluation board is designed to facilitate
a quick evaluation of the device. The default populated
evaluation board will have a gain of two.
This evaluation board manual contains:
Information on OP1SOT23EVB (SOT23 package)
www.DataSheet4U.com Evaluation Board
Information on OP1SC70EVB (SC70 package)
Evaluation Board
Information on OP1SOIC8EVB (SOIC8 package)
Evaluation Board
Bill of Materials
Board Lay−up
The SOT23, SC70, and SOIC8 evaluation boards are
implemented in two layers (Figure 1, Evaluation Board
Lay−up). The first layer is the 1.0 oz copper ground plane,
where a portion of the ground plane is cut out to mount the
device. The FR4 dielectric material is placed between the
first and second layer. The second layer contains the rest of
the components and primary signal traces.
Top Silkscreen
Top Soldermask
Top Plating
01 Cu = 1 Oz, 0.0014
Top Metal
Adjust
02
Tw = 0.045, Zo = 50 W, Cu = 1 Oz, 0.0014
Bottom Metal
Bottom Plating
Bottom Soldermask
Bottom Silkscreen
Figure 1. Evaluation Board Lay−up
Board Design
The evaluation board was designed for non−inverting op
amp configuration (Figure 2). The input contains
termination resistor R3 (usually 50 Ω). The input can also be
monitored through J1 when R1 and R2 are populated. The
evaluation board has versatile loading options for the op
amp through C9, R10, and R11 depending on the user’s
preference it can be configured as capacitive load, series
resistance load, parallel resistance load, etc.
© Semiconductor Components Industries, LLC, 2005
July, 2005 − Rev. 0
1
Publication Order Number:
OPAMP1EVB/D



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VCC OA
Banana Jack
J5
Ferrite Bead
L2
OPAMP1EVB
GND
Banana Jack
VCC J7 VEE
Ferrite Bead VEE OA
L1 Banana Jack
J6
D6 C7 C6 C5
R7
C3 C2
C1
R5
D7
BNC Connector
Scope
J1
R1
R2
BNC Connector
IN
J2
R3
EN
JMP1
+
VEE VCC
R6
R4
R10
C9
BNC Connector
Out
R11 J3
Figure 2. Evaluation Board Schematic
L1, L2, C1, C2, C3, C5, C6, C7, D6, D7, R5, and R7
are for power supply noise suppression
R3 is for input matching of 50 W trace
R1 and R2 are for monitoring the input signal
R4 and R6 are for feedback resistors
C9, R10, and R11 are for different loading
configuration of the op amp
If enable pin is available, the Jumper 1 can be used to
enable or disable the device
http://onsemi.com
2



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OPAMP1EVB
Board Layout
Figure 3 shows the board layout of the SOT23 package (SC70 board layout is similar to SOT23 board layout) and Figure 4
shows the board layout of the SOIC8 package.
Top View
Bottom View
Figure 3. SOT23 Evaluation Board Layout
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3



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OPAMP1EVB
Top View
Bottom View
Figure 4. SOIC−8 Evaluation Board Layout
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4



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ON Semiconductor
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