NVT2006 Datasheet PDF - NXP

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NVT2006
NXP

Part Number NVT2006
Description (NVT2003 - NVT2006) Bidirectional voltage-level translator
Page 27 Pages


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NVT2003/04/06
Bidirectional voltage-level translator for open-drain and
push-pull applications
Rev. 4 — 7 September 2012
Product data sheet
1. General description
The NVT2003/04/06 is a family of bidirectional voltage level translators operational from
1.0 V to 3.6 V (Vref(A)) and 1.8 V to 5.5 V (Vref(B)), which allow bidirectional voltage
translations between 1.0 V and 5 V without the need for a direction pin in open-drain or
push-pull applications. Bit widths ranging from 3-bit to 6-bit are offered for level translation
application with transmission speeds < 33 MHz for an open-drain system with a 50 pF
capacitance and a pull-up of 197 .
When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the An and Bn ports. The low ON-state resistance (Ron) of the
switch allows connections to be made with minimal propagation delay. Assuming the
higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is
limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to the
drain pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control.
When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O,
respectively, allowing bidirectional data flow between ports. When EN is LOW, the
translator switch is off, and a high-impedance state exists between ports. The EN input
circuit is designed to be supplied by Vref(B). To ensure the high-impedance state during
power-up or power-down, EN must be LOW.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits
Provides bidirectional voltage translation with no direction pin
Less than 1.5 ns maximum propagation delay
Allows voltage level translation between:
1.0 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)
1.2 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)
1.8 V Vref(A) and 3.3 V or 5 V Vref(B)
2.5 V Vref(A) and 5 V Vref(B)
3.3 V Vref(A) and 5 V Vref(B)
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NXP Semiconductors
NVT2003/04/06
Bidirectional voltage-level translator
Low 3.5 ON-state connection between input and output ports provides less signal
distortion
5 V tolerant I/O ports to support mixed-mode signal operation
High-impedance An and Bn pins for EN = LOW
Lock-up free operation
Flow through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 3.5 kV HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Packages offered: TSSOP10, HXSON12, DHVQFN16, HVQFN16, TSSOP16
3. Ordering information
Table 1. Ordering information
Tamb = 40 C to +85 C.
Type number Topside
mark
Number
of bits
Package
Name
Description
Version
NVT2003DP N2003
3
TSSOP10 plastic thin shrink small outline package; 10 leads;
body width 3 mm
SOT552-1
NVT2004TL N04
4
HXSON12
plastic, thermal enhanced extremely thin small outline SOT973-2
package; no leads; 12 terminals;
body 1.35 2.5 0.5 mm
NVT2006BQ N2006
6
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
NVT2006BS N06
6
HVQFN16 plastic thermal enhanced very thin quad flat package; SOT758-1
no leads; 16 terminals; body 3 3 0.85 mm
NVT2006PW NVT2006 6
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
4. Functional diagram
VREFA VREFB
NVT20xx
EN
A1 SW B1
An SW Bn
GND
002aae132
Fig 1. Logic diagram of NVT2003/04/06 (positive logic)
NVT2003_04_06
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 7 September 2012
© NXP B.V. 2012. All rights reserved.
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NXP Semiconductors
5. Pinning information
5.1 Pinning
5.1.1 3-bit in TSSOP10 package
NVT2003/04/06
Bidirectional voltage-level translator
GND 1
VREFA 2
A1 3
A2 4
A3 5
NVT2003DP
10 EN
9 VREFB
8 B1
7 B2
6 B3
002aae836
Fig 2. Pin configuration for TSSOP10
5.1.2 4-bit in HXSON12 package
NVT2004TL
GND 1
12 EN
VREFA 2
11 VREFB
A1 3
10 B1
A2 4
9 B2
A3 5
8 B3
A4 6
7 B4
002aae219
Transparent top view
Fig 3. Pin configuration for HXSON12U
NVT2003_04_06
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 7 September 2012
© NXP B.V. 2012. All rights reserved.
3 of 27
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NXP Semiconductors
NVT2003/04/06
Bidirectional voltage-level translator
5.1.3 6-bit in TSSOP16, DHVQFN16 and HVQFN16 packages
GND 1
VREFA 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
NVT2006PW
16 EN
15 VREFB
14 B1
13 B2
12 B3
11 B4
10 B5
9 B6
002aae220
Fig 4. Pin configuration for TSSOP16
terminal 1
index area
VREFA 2
15 VREFB
A1 3
14 B1
A2 4
13 B2
NVT2006BQ
A3 5
12 B3
A4 6
11 B4
A5 7
10 B5
002aae221
Transparent top view
Fig 5. Pin configuration for DHVQFN16
terminal 1
index area
A1 1
A2 2
A3 3
A4 4
NVT2006BS
12 B1
11 B2
10 B3
9 B4
Transparent top view
Fig 6. Pin configuration for HVQFN16
002aae222
NVT2003_04_06
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 7 September 2012
© NXP B.V. 2012. All rights reserved.
4 of 27
Free Datasheet http://www.datasheet4u.com/



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