NJU26207 Datasheet PDF - New Japan Radio

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NJU26207
New Japan Radio

Part Number NJU26207
Description Dolby Volume Decoder
Page 9 Pages


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Dolby Volume Decoder
General Description
The NJU26207 is a digital signal processor that provides the function of Dolby Volume.
Dolby Volume solves volume level difference among channels, input sources and etc.
The mix balance is reproduced by high or low volume level.
The applications of NJU26207 are suitable for Digital TV, Front Surround Speaker and
speakers system.
Package
Features
-Software
Dolby Volume (512FFT Window / 20Band)
Delay
Master Volume / Balance Control
Sampling Frequency : 32kHz, 44.1kHz, 48kHz
2 Input channels, 2 Output channels
NJU26207V
-Hardware
24bit Fixed-point Digital Signal Processing
Maximum Clock Frequency : 12.288MHz(Standard), built-in PLL Circuit
Digital Audio Interface
: 4 Input ports / 3 Output ports
Digital Audio Format
: I2S 24bit, left-justified, right-justified, BCK : 32fs/64fs
Master / Slave Mode
Microcomputer Interface
I2C Bus (Standard-mode/100kbps, Fast-mode/400kbps)
4-Wire Serial Bus (4-Wire: Clock, Enable, Input data, Output data)
Operating Voltage
Input Terminal
: VDD = VDDPLL = 1.8V
: VDDIO = 3.3V
: +5.0V Input tolerant
Package
: SSOP44 (Pb-Free)
* The detail hardware specification of the NJU26207 is described in the “ NJU26200 Series Hardware Data Sheet”.
Ver.2008-12-03
-1-



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NJU26207
Hardware Block Diagram
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AD1/SDIN AD2/SSb
SCL/SCK
SDA/SDOUT
RESETb
MCK
CLK
CLKOUT
SERIAL
HOST
INTERFACE
TIMING
GENERATOR
/ PLL
DSP ARITHMETIC UNIT
PROGRAM
CONTROL
ALU
24-BIT 24-BIT
MULTIPLIER
ADDRESS GENERATION UNIT
SERIAL AUDIO
INTERFACE
L/Rout
(L+R)/2out
Monitor L/R
in
DATA
RAM
FIRMWARE
ROM
General I/O
INTERFACE
Fig. 1 NJU26207 Hardware Block Diagram
BCKO
LRO
SDO0
SDO1
SDO2
SDI0~3
BCKI
LRI
PROC
MUTEb
SEL
WDC
Function Block Diagram
L/R(SDI0)
L/R(SDI1)
L/R(SDI2)
L/R(SDI3)
Delay
Dolby
Volume
L/R(SDO0)
(L+R)/2(SDO1)
Monitor L/R(SDO2)
Fig. 2 NJU26207 Function Block Diagram (Firmware)
-2-
Ver.2008-12-03



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Pin Configuration
SDI3
SDI2
SDI1
SDI0
LRI
VDDIO
BCKI
VSS
VDD
TEST
MUTEb
WDC
PROC
VSSIO
VDDIO
SEL
VDDPLL
VSSPLL
VSS
VDD
CLKOUT
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NJU26207
SSOP44
NJU26207www.DataSheet4U.com
44 VDD
43 VSS
42 VSSIO
41 VDDIO
40 SDO0
39 SDO1
38 SDO2
37 TEST
36 LRO
35 BCKO
34 MCK
33 VDDIO
32 SDA/SDOUT
31 SCL/SCK
30 AD2/SSb
29 AD1/SDIN
28 TEST
27 TEST
26 TEST
25 RESETb
24 VDDIO
23 VSSIO
Fig. 3 NJU26207 Pin Configuration
Ver.2008-12-03
-3-



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NJU26207
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Pin Description
Table 1 Pin Description
Pin No.
Symbol
1 SDI3
2 SDI2
3 SDI1
4 SDI0
5 LRI
6 VDDIO
7 BCKI
8 VSS
9 VDD
10 TEST *
11 MUTEb *
12 WDC *
13 PROC *
14 VSSIO
15 VDDIO
16 SEL
17 VDDPLL
18 VSSPLL
19 VSS
20 VDD
21 CLKOUT
22 CLK
23 VSSIO
24 VDDIO
25 RESETb
26 TEST
27 TEST
28 TEST
29 AD1/SDIN
30 AD2/SSb
31 SCL/SCK
32 SDA/SDOUT
33 VDDIO
34 MCK
35 BCKO
36 LRO
37 TEST
38 SDO2
39 SDO1
40 SDO0
41 VDDIO
42 VSSIO
43 VSS
44 VDD
I/O Function
I Audio Data Input ch.3 (L/R)
I Audio Data Input ch.2 (L/R)
I Audio Data Input ch.1 (L/R)
I Audio Data Input ch.0 (L/R)
I LR Clock Input
- I/O Power Supply +3.3V
I Bit Clock Input
- DSP Core Power Supply GND
- DSP Core Power Supply +1.8V
I
for test
connect with VSSIO through 3.3-ohm resistance.
I Master Volume Status after reset ‘1’: 0dB, ‘0’: Mute
OD Watchdog Clock output pin (Open drain output)
I
Signal Processing after reset ‘1’: Normal Processing, ‘0’: Waiting for a
Command without Processing
- I/O Power Supply GND
- I/O Power Supply +3.3V
I Host Interface Selection ‘1’: Serial Interface, ‘0’: I2C bus
- PLL Power Supply +1.8V
- PLL Power Supply GND
- DSP Core Power Supply GND
- DSP Core Power Supply +1.8V
O OSC Clock Output
I OSC Clock Input (12.288MHz)
- I/O Power Supply GND
- I/O Power Supply +3.3V
I Reset (RESETb=’0’: DSP Reset)
I for test (connect to VDDIO)
I for test (connect to VSSIO)
I for test (connect to VSSIO)
I I2C Address (I2C mode) / Serial In (4-wire serial mode)
I I2C Address (I2C mode) / Serial enable (4-wire serial mode)
I I2C SCL (I2C mode) / Serial clock (4-wire serial mode)
I/O I2C SDA (I2C mode) / Serial Out (4-wire serial mode)
- I/O Power Supply +3.3V
O A/D, D/A clock output (buffer output of a CLK pin)
O Bit Clock Output
O LR Clock Output
O For test (Non connect)
O Audio Data Output ch.2 (Monitor L/R)
O Audio Data Output ch.1 ((L+R)/2)
O Audio Data Output ch.0 (L/R)
- I/O Power Supply +3.3V
- I/O Power Supply GND
- DSP Core Power Supply GND
- DSP Core Power Supply +1.8V
Note : I : Input
O : Output
OD : Open Drain Output
I/O : Bi-directional
Pins symbol with * : Connect with VDDIO or VSSIO through 3.3kresistance
-4-
Ver.2008-12-03



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