MV3507 Datasheet PDF - Zarlink Semiconductor

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MV3507
Zarlink Semiconductor

Part Number MV3507
Description (MV3506 - MV3508) FILTER/CODEC
Page 14 Pages


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MV3506/7/8
ADVANCE INFORMATION
DS3133-2.1
MV3506 A-LAW FILTER/CODEC
MV3507 µ-LAW FILTER/CODEC
MV3508 A-LAW FILTER/CODEC WITH OPTIONAL SQUELCH
These devices are silicon gate CMOS Companding
Encoder/Decoder integrated circuits designed to implement
the per channel voice frequency Codecs used in PCM
systems. They contain the band-limiting filters and the analog
to digital conversion circuits that conform to the desired
transfer characteristic. The MV3506 and MV3508 provide the
European A-Law companding and the MV3507 provides the
North American µ-Law companding characteristic. The
MV3508 has programmable squelch circuitry to reduce idle
channel noise.
These circuits provide the interface between the analog
signals of the subscriber loop and digital signals of the PCM
highway in a digital telephone switching system. The devices
operate from dual power supplies of ±5V.
FEATURES
s Low Power CMOS 80mW (Operating) 10mW (Standby)
s Meets or Exceeds AT & T3, and CCITT G.711, G.712 and
G.733 Specifications
s Input Analog Filter Eliminates Need for External Anti-
aliasing Prefilter
s Uncommitted Input and Output Op. Amps for
Programming Gain
s Output Op. Amp Provides ±3.1V into a 1200 Ohms Load
or can be Switched Off for Reduced Power (70mW)
s Encoder has Dual-speed Auto-zero Loop for Fast
Acquisition on Power-up
s Low Absolute Group Delay = 410 microseconds at 1 kHz
TST/SE
CLK SEL
T SHIFT
SYS CLK
T STROBE
PCM OUT
D GND
CAZ
R SHIFT
R STROBE
PCM IN
1 22
2 21
3 20
4 19
5 MV3506/ 18
6 7/8 17
7 16
8 15
9 14
10 13
11 12
VDD
VOUT
OUT-
FLT OUT
PDB
VIN
IN-
IN+
CAZ GND
A GND
VSS
DG22
Figure 1: Pin connection - top view
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MV3506/7/8
FUNCTIONAL DESCRLPTION
Fig.2 shows the simplified block diagram of the devices.
They contain independent circuitry for processing transmit and
receive signals. Switched capacitor filters provide the
necessary bandwidth limiting of voice signals in both
directions. Circuitry for coding and decoding operates on the
principle of successive approximation, using charge
redistribution in a binary weighted capacitor array to define
segments and a resistor chain to define steps.
TRANSMIT SECTION
Input analog signals first enter the chip at the uncommitted
op.amp. terminals (IN+ and IN- pins). This allows for the gain in
the system to be trimmed. From the VIN pin the signal enters a
second-order analog anti-aliasing filter. This filter eliminates
the need for any off-chip filtering as it provides attenuation of
34dB (typically) at 256kHz and 44dB (typically) at 512kHz.
The signal next enters the transmit filter, which is a fifth
order low-pass filter clocked at 256kHz, followed by a third
order high-pass filter clocked at 64kHz. The resulting
bandpass characteristics meet the CCITT specifications
G.711, G.712 and G.733. Some representative attenuations
are better than 26dB from 0 to 60Hz and better than 35dB from
4.6kHz to 100kHz.
The output of the transmit filter is sampled at the analog to
digital encoder by a capacitor array at the sampling rate of
8kHz. The successive approximation conversion process
requires about 72µsec.
The 8-bit PCM data is clocked out by the transmit shift
clock which can vary from 64kHz to 2.048MHz in 8kHz steps
(see Figs. 3 and 4). A switched capacitor dual-speed, autozero
loop using a small non-critical external capacitor (0.1µF)
provides DC offset cancellation by integrating the sign bit of
the PCM data and feeding it back to the noninverting input of
the comparator.
Included in the circuitry of the MV3507 is ‘All Zero’ code
suppression so that negative input signal values between
decision values numbers 127 and 128 are encoded as
00000010. This prevents loss of repeater synchronisation by
DS1 (T1 ) line clock recovery circuitry as there are never
more than 15 consecutive zeros.
An additional feature of the MV3506/7 is a special circuit to
eliminate any transmitted idle channel noise during quiet
periods. When the input of these chips is-such that for 250ms
the only code words generated were +0, -0, +1 or -1, the output
word will be a +0. The steady +0 state prevents alternating sign
bits or LSB from toggling and thus results in a quieter signal at
the decoder. Upon detection of a different value, the output
resumes normal operation resetting the 250ms timer. This
feature is a form of idle Channel Noise ‘Squelch’ or ‘Crosstalk
Suppression’. It is of particular importance in the MV3506 A-
Law version because the A-Law transfer characteristic has
‘mid-riser’ bias which enhances low level signals from
crosstalk.
RECEIVE SECTION
A receive shift clock, variable between the frequencies of
64kHz and 2.048MHz clocks the PCM data into the input buffer
register once every sampling period (see Figs.5 and 6). A
charge proportional to the received PCM data word appears
on the decoder capacitor array of the digital to analog
converter. A sample and hold circuit, initialised to zro by a
narrow pulse at the beginning of each sampling period,
integrates the charge and holds it for the rest of the sampling
period .
The receive filter, consisting of a switched-capacitor
fiHhorder low-pass filter clocked at 256kHz, smooths the
sampled and held signal. It also performs the loss equalisation
to compensate for the sin(x)/x distortion due to the sampling.
The filter output (FLT OUT pin) is available for driving
electronic hybrids directly as long as the impedance is greater
than 20k. When used in this fashion the low impedance
output amp can be switched off for a considerable saving in
power consumption. When it is required to drive a 600load
the output amp allows gain trimming as well as impedance
matching.
VIN PDB
TST/SE
CAZ CAZ GND
17(21)
18(22)
15(19)
IN+ +
16(20)
IN- -
ANTI-ALIASING
FILTER
CLK SEL
SYS CLK
2(3)
4(5)
CLOCK
GENERATOR
VOUT
21(25)
-
+
1(28)
TRANSMIT
FILTER
RECEIVE
FILTER
8(11) 14(18)
A TO D
ENCODER
TRANSMIT
INTERFACE
5(6)
T STROBE
3(4)
T SHIFT
6(7)
PCM OUT
(26)
TA/BSEL
(2)
A IN
(1)
B IN
D TO A
DECODER
RECEIVE
INTERFACE
10(14)
9(13)
11(15)
(12)
(10)
(9)
R STROBE
R SHIFT
PCM IN
RA/B SEL
A OUT
B OUT
20(24)
19(23) 13(17)
12(16)
7(8)
OUT- FLT OUT A GND VSS D GND
22(27)
VDD
Figure 2: Functional block diagram (pin numbers for the MV3507A are in brackets)
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SYS CLK
T STROBE
T STROBE
T SHIFT
PCM OUT
SYS CLK
R STROBE
Figure 3: Transmit strobe alignment
1234 5678
Figure 4: Transmit alignment
Figure 5: Receive strobe alignment
MV3506/7/8
R STROBE
R SHIFT
PCM IN
1234 5678
Figure 6: Receive alignment
TIMING REQUIREMENTS
The internal design of the devices paid careful attention to
the timing requirements of various systems. In North America,
central office and channel bank designs often follow the
American Telephone and Telegraph Company’s T1 (DS1)
Carrier PCM format to multiplex 24 voice channels at a data
rate of 1.544M b/s. PABX designs, on the other hand, may use
their own multiplexing formats with different data rates.
Nevertheless, in digital telephone designs, Codecs may be
used in a non-multiplexed form with data rate as low as 64kbit/
s. The µ-Law Codecs fulfil these requirements.
In Europe, telephone exchange and channel bank designs
often follow the CCITT carrier PCM format to multiplex 30
telephony channels at a data rate of 2.048Mbit/s. The A-Law
Codecs are designed for this market and will also handle
PABX and digital telephone applications.
The timing format chosen for the devices allows operation
in both multiplexed or non-multiplexed form with data rates
variable from 64kbit/s to 2.048Mbit/s. Use of separate internal
clocks for filters and for shifting of PCM input/output data
allows for this variation.
The devices do not require that the 8kHz transmit and
receive sampling strobes be exactly 8 bit periods wide. The
device has an internal bit counter that counts the number of
data bits shifted. It is reset on the leading ( +ve) edges of the
strobe, forcing the PCM output into its high impedance state
after the 8th bit is shifted out. This allows the width of the
strobe signal to vary as long as its repetition rate is 8kHz and
the transmit and receive shift clocks are synchronised to it.
SYSTEM CLOCK
The basic timing is provided by the system clock which is
divided down internally to provide the various filter clocks and
the timing for the conversions. The transmit and receive
strobes and clocks must be locked to this clock so that the
PCM data matches the sample rates.
3



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