MTW26N15E Datasheet PDF - Motorola

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MTW26N15E
Motorola

Part Number MTW26N15E
Description TMOS POWER FET
Page 8 Pages


MTW26N15E datasheet pdf
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTW26N15E/D
Designer's
Data Sheet
TMOS E-FET .
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
www.DataSheet4cUo.nctormols, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware
G
®
D
S
MTW26N15E
Motorola Preferred Device
TMOS POWER FET
26 AMPERES
150 VOLTS
RDS(on) = 0.095 OHM
CASE 340K–01, Style 1
TO–247AE
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 M)
Gate–Source Voltage — Continuous
— Non–Repetitive (tp 10 ms)
VDSS 150 Vdc
VDGR 150 Vdc
VGS
± 20 Vdc
VGSM ± 40 Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation
Derate above 25°C
ID 26 Adc
ID 19.4
IDM 78 Apk
PD 150 Watts
1.2 W/°C
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, IL = 26 Apk, L = 2.4 mH, RG = 25 )
EAS 810 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
RθJC
RθJA
0.83 °C/W
62.5
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1



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MTW26N15E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
150
21
— Vdc
— mV/°C
Zero Gate Voltage Drain Current
(VDS = 150 Vdc, VGS = 0 Vdc)
(VDS = 150 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
IDSS
IGSS
µAdc
— — 10
— — 100
— — 100 nAdc
VGS(th)
2.0 — 4.0 Vdc
— 7.0 — mV/°C
www.DataSheet4US.ctoamtic Drain–Source On–Resistance (VGS = 10 Vdc, ID = 13 Adc)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 26 Adc)
(ID = 13 Adc, TJ = 125°C)
Forward Transconductance (VDS = 10 Vdc, ID = 13 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
(VDD = 75 Vdc, ID = 26 Adc,
VGS = 10 Vdc,
RG = 9.1 )
Gate Charge
(See Figure 8)
(VDS = 120 Vdc, ID = 26 Adc,
VGS = 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 26 Adc, VGS = 0 Vdc)
(IS = 26 Adc, VGS = 0 Vdc, TJ = 125°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
— 0.078 0.095 Ohm
Vdc
— 2.2 3.12
— — 2.47
7.0 —
— mhos
1850
2500
pF
— 450 750
— 95 200
— 17 40 ns
— 116 200
— 48 100
— 69 140
— 48 100 nC
— 11 —
— 22 —
— 19 —
Vdc
— 0.98 1.47
— 0.88 —
Reverse Recovery Time
(See Figure 14)
(IS = 26 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
trr
ta
tb
QRR
LD
— 198 —
ns
— 118 —
— 80 —
— 1.5 — µC
— 4.5 — nH
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
LS
— 13 — nH
2 Motorola TMOS Power MOSFET Transistor Device Data



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TYPICAL ELECTRICAL CHARACTERISTICS
MTW26N15E
70
TJ = 25°C
60
50
VGS = 10 V
9.0 V
8.0 V
40
7.0 V
30
20 6.0 V
10
0
0
www.DataSheet4U.com
5.0 V
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
10
90
80 VDS 10 V
70
TJ = – 55°C
25°C
60
50 100°C
40
30
20
10
0
2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
10
Figure 2. Transfer Characteristics
0.2
0.18 VGS = 10 V
0.16
0.14 TJ = 100°C
0.12
0.1
25°C
0.08
0.06
– 55°C
0.04
0.02
0 4.0 8.0 12 16 20 24 28 32 36 40 44 48 52
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
0.105
0.1
TJ = 25°C
0.095
0.09
0.085
VGS = 10 V
0.08
0.075
15 V
0.07
0.065
5 10 15 20 25 30 35 40 45 50 55
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2.2
2.0 VGS = 10 V
ID = 13 A
1.8
1.6
1.4
1.2
1.0
0.8
0.6
– 50 – 25
0 25 50 75 100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 5. On–Resistance Variation with
Temperature
150
1000
VGS = 0 V
100
10
TJ = 125°C
100°C
25°C
1.0
0 25 50 75 100 125 150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3



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MTW26N15E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
www.DataSheet4thUe.cpomlateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
5000
VDS = 0 V
4000
VGS = 0 V
TJ = 25°C
3000 Crss
2000
Ciss
1000
0
10
505
VGS VDS
Coss
Crss
10 15 20
25
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4 Motorola TMOS Power MOSFET Transistor Device Data



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