MTW24N40E Datasheet PDF - Motorola

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MTW24N40E
Motorola

Part Number MTW24N40E
Description TMOS POWER FET 24 AMPERES 400 VOLTS
Page 8 Pages


MTW24N40E datasheet pdf
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTW24N40E/D
Designer's
Data Sheet
TMOS E-FET .
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
www.DataSheet4dUra.cionm–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware
G
®
D
S
MTW24N40E
Motorola Preferred Device
TMOS POWER FET
24 AMPERES
400 VOLTS
RDS(on) = 0.16 OHM
CASE 340K–01, Style 1
TO–247AE
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 M)
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp 10 ms)
VDSS
VDGR
VGS
VGSM
400
400
± 20
± 40
Vdc
Vdc
Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
ID 24 Adc
ID 17.7
IDM 72 Apk
Total Power Dissipation
Derate above 25°C
PD 250 Watts
2.0 W/°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 )
TJ, Tstg
EAS
– 55 to 150
600
°C
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
RθJC
RθJA
0.50 °C/W
40
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1



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MTW24N40E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
400
360
— Vdc
— mV/°C
Zero Gate Voltage Drain Current
(VDS = 400 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
IDSS
IGSS
µAdc
— — 10
— — 100
— — 100 nAdc
VGS(th)
2.0 — 4.0 Vdc
— 7.0 — mV/°C
www.DataSheet4US.ctoamtic Drain–Source On–Resistance (VGS = 10 Vdc, ID = 12 Adc)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 24 Adc)
(ID = 12 Adc, TJ =125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 12 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
(VDD 200= Vdc, ID = 24 Adc,
VGS = 10 Vdc,
RG = 9.1 )
Gate Charge
(See Figure 8)
(VDS = 320 Vdc, ID = 24 Adc,
VGS = 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 24 Adc, VGS = 0 Vdc)
(IS = 24 Adc, VGS = 0 Vdc, TJ = 125°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
— 0.13 0.16 Ohm
Vdc
— — 4.5
— — 4.3
11 17 — mhos
4000
5600
pF
— 530 740
— 112 220
— 32 60 ns
— 96 204
— 99 194
— 92 186
— 98 160 nC
— 24 —
— 38 —
— 40 —
Vdc
— 0.94 1.5
— 0.9 —
Reverse Recovery Time
(See Figure 14)
Reverse Recovery Stored Charge
(IS = 24 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
trr
ta
tb
QRR
— 372 —
ns
— 244 —
— 128 —
— 5.3 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
LD — 4.5 — nH
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
LS
— 13 — nH
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
2 Motorola TMOS Power MOSFET Transistor Device Data



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50
TJ = 25°C
40
30
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V
7V
6V
9V
8V
50
VDS 10 V
40
30
MTW24N40E
20 20
10
0
0
www.DataSheet4U.com
5V
4V
2.0 4.0 6.0 8.0
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
10
10 25°C
100°C
0 TJ = – 55°C
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0.4
VGS = 10 V
0.35
0.3 TJ = 100°C
0.25
0.2
0.15 25°C
0.1 – 55°C
0.05
0
0 10 20 30 40 50
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
0.19
TJ = 25°C
0.18
0.17
0.16
VGS = 10 V
0.15
15 V
0.14
0.13
0.12
0
10 20 30 40
ID, DRAIN CURRENT (AMPS)
50
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
3.0
VGS = 10 V
2.5 ID = 12 A
2.0
1.5
1.0
0.5
0
– 50 – 25
0 25 50 75 100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 5. On–Resistance Variation with
Temperature
150
10000
VGS = 0 V
1000
100
TJ = 125°C
100°C
10
25°C
1
0 100 200 300 400
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3



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MTW24N40E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
www.DataSheet4thUe.cpomlateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
9000
Ciss
8000
7000
VDS = 0 V
VGS = 0 V
TJ = 25°C
6000
5000 Crss
4000
Ciss
3000
2000
1000
0
10
Crss
505
VGS VDS
Coss
10 15 20 25
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
10000
VGS = 0 V
TJ = 25°C
1000
100
Ciss
Coss
Crss
10
10
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Variation
1000
4 Motorola TMOS Power MOSFET Transistor Device Data



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