MTV32N20E Datasheet PDF - Motorola

www.Datasheet-PDF.com

MTV32N20E
Motorola

Part Number MTV32N20E
Description TMOS POWER FET 32 AMPERES 200 VOLTS RDS(on) = 0.075 OHM
Page 10 Pages


MTV32N20E datasheet pdf
Download PDF
MTV32N20E pdf
View PDF for Mobile

No Preview Available !

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
TMOS E-FET.
Power Field Effect Transistor
D3PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
speed switching applications in power supplies, converters, PWM
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
D
N–Channel
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
G
®
S
Order this document
by MTV32N20E/D
MTV32N20E
TMOS POWER FET
32 AMPERES
200 VOLTS
RDS(on) = 0.075 OHM
CASE 433–01, Style 2
D3PAK Surface Mount
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 M)
Gate–to–Source Voltage — Continuous
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 32 Apk, L = 1.58 mH, RG = 25 )
VDSS
VDGR
VGS
ID
ID
IDM
PD
TJ, Tstg
EAS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
RθJC
RθJA
RθJA
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TL
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Value
200
200
±20
32
19
128
180
1.44
2.0
– 55 to 150
810
0.7
62.5
35
260
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
°C
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1



No Preview Available !

MTV32N20E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
200
247
Vdc
— mV/°C
Zero Gate Voltage Drain Current
(VDS = 200 Vdc, VGS = 0 Vdc)
(VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
IDSS
IGSS
µAdc
— — 250
— — 1000
— — 100 nAdc
VGS(th)
2.0 3.0 4.0 Vdc
— 8.0 — mV/°C
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 16 Adc)
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 32 Adc)
(VGS = 10 Vdc, ID = 16 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 16 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
(VDD = 100 Vdc, ID = 32 Adc,
VGS = 10 Vdc,
RG = 6.2 )
Gate Charge
(See Figure 8)
(VDS = 160 Vdc, ID = 32 Adc,
VGS = 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 32 Adc, VGS = 0 Vdc)
(IS = 32 Adc, VGS = 0 Vdc, TJ = 125°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
— 0.064 0.075 Ohm
Vdc
— 2.1 3.0
— — 2.7
12 20 — mhos
3600
5000
pF
— 130 250
— 690 1000
— 25 50 ns
— 120 240
— 75 150
— 91 182
— 85 120 nC
— 12 —
— 40 —
— 30 —
Vdc
— 1.1 2.0
— 0.9 —
Reverse Recovery Time
(IS = 32 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
trr
ta
tb
QRR
LD
— 280 —
— 195 —
— 85 —
— 2.94 —
— 5.0 —
ns
µC
nH
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
LS
nH
— 13 —
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
2 Motorola TMOS Power MOSFET Transistor Device Data



No Preview Available !

TYPICAL ELECTRICAL CHARACTERISTICS
MTV32N20E
100
TJ = 25°C
80
VGS = 10 V
9V
8V
50
wVDS 10 V
40
TJ = –55°C
25°C
100°C
60 30
7V
40
6V
20
5V
0
0 1 2 3 4 5 6 7 8 9 10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
20
10
0
0 2 4 6 8 10
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0.16
VGS = 10 V
0.14
0.12
TJ = 100°C
0.10
0.08 25°C
0.06
– 55°C
0.04
0.02
0
0 8 16 24 32 40 48 56 64
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
0.10
TJ = 25°C
0.09
0.08
0.07 VGS = 10 V
15 V
0.06
0.05
0 8 16 24 32 40 48 56 64
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2.5
VGS = 10 V
ID = 16 A
2.0
1.5
1.0
0.5
–50
–25 0
25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
150
10000
VGS = 0 V
1000
TJ = 125°C
100
100°C
25°C
10
0 50 100 150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
200
Motorola TMOS Power MOSFET Transistor Device Data
3



No Preview Available !

MTV32N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
10000
VDS = 0 V VGS = 0 V
8000
Crss
6000
TJ = 25°C
4000 Ciss
2000
Coss
0
10 5 0 5 10 15 20 25
VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4 Motorola TMOS Power MOSFET Transistor Device Data



MTV32N20E datasheet pdf
Download PDF
MTV32N20E pdf
View PDF for Mobile


Related : Start with MTV32N20 Part Numbers by
MTV32N20E TMOS POWER FET 32 AMPERES 200 VOLTS RDS(on) = 0.075 OHM MTV32N20E
Motorola
MTV32N20E pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact