MT4LDT464H Datasheet PDF - Micron Technology

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MT4LDT464H
Micron Technology

Part Number MT4LDT464H
Description SMALL-OUTLINE DRAM MODULE
Page 30 Pages


MT4LDT464H datasheet pdf
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SMALL-OUTLINE
DRAM MODULE
4, 8 MEG x 64
DRAM SODIMMs
MT4LDT464H (X)(S), MT8LDT864H (X)(S)
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/datasheets/datasheet.html
FEATURES
• JEDEC pinout in a 144-pin, small-outline, dual in-
line memory module (SODIMM)
• 32MB (4 Meg x 64) and 64MB (8 Meg x 64)
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All inputs, outputs and clocks are TTL-compatible
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
• FAST PAGE MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• Optional Self Refresh Mode (S)
• Serial presence-detect (SPD)
OPTIONS
• Package
144-pin SODIMM (gold)
MARKING
G
• Timing
50ns access
60ns access
-5
-6
• Access Cycles
FAST PAGE MODE
EDO PAGE MODE
None
X
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
*Contact factory for availability
None
S*
KEY TIMING PARAMETERS
FPM Operating Mode
SPEED
-5
-6
tRC
90ns
110ns
tRAC
50ns
60ns
tPC
30ns
35ns
tAA
25ns
30ns
tCAC
13ns
15ns
tRP
30ns
40ns
EDO Operating Mode
SPEED
-5
-6
tRC
84ns
104ns
tRAC
50ns
60ns
tPC
20ns
25ns
tAA
25ns
30ns
tCAC
13ns
15ns
tCAS
8ns
10ns
PIN ASSIGNMENT (Front View)
144-Pin Small-Outline DIMM
(I-1; 32MB)
(I-2; 64MB)
PIN FRONT PIN BACK PIN FRONT PIN BACK
1 VSS 2 VSS 73 OE# 74 RFU
3 DQ0 4 DQ32 75 VSS 76 VSS
5 DQ1 6 DQ33 77 RSVD 78 RSVD
7 DQ2 8 DQ34 79 RSVD 80 RSVD
9 DQ3 10 DQ35 81 VDD 82 VDD
11 VDD 12 VDD 83 DQ16 84 DQ48
13 DQ4 14 DQ36 85 DQ17 86 DQ49
15 DQ5 16 DQ37 87 DQ18 88 DQ50
17 DQ6 18 DQ38 89 DQ19 90 DQ51
19 DQ7 20 DQ39 91 VSS 92 VSS
21 VSS 22 VSS 93 DQ20 94 DQ52
23 CAS0# 24 CAS4# 95 DQ21 96 DQ53
25 CAS1# 26 CAS5# 97 DQ22 98 DQ54
27 VDD 28 VDD 99 DQ23 100 DQ55
29 A0 30 A3 101 VDD 102 VDD
31 A1 32 A4 103 A6 104 A7
33 A2 34 A5 105 A8 106 A11
35 VSS 36 VSS 107 VSS 108 VSS
37 DQ8 38 DQ40 109 A9 110 NC (A12)
39 DQ9 40 DQ41 111 A10 112 NC (A13)
41 DQ10 42 DQ42 113 VDD 114 VDD
43 DQ11 44 DQ43 115 CAS2# 116 CAS6#
45 VDD 46 VDD 117 CAS3# 118 CAS7#
47 DQ12 48 DQ44 119 VSS 120 VSS
49 DQ13 50 DQ45 121 DQ24 122 DQ56
51 DQ14 52 DQ46 123 DQ25 124 DQ57
53 DQ15 54 DQ47 125 DQ26 126 DQ58
55 VSS 56 VSS 127 DQ27 128 DQ59
57 RSVD 58 RSVD 129 VDD 130 VDD
59 RSVD 60 RSVD 131 DQ28 132 DQ60
61 RFU 62 RFU 133 DQ29 134 DQ61
63 VDD 64 VDD 135 DQ30 136 DQ62
65 RFU 66 RFU 137 DQ31 138 DQ63
67 WE# 68 RFU 139 VSS 140 VSS
69 RAS0# 70
NC 141 SDA 142 SCL
71 NC 72 NC 143 VDD 144 VDD
NOTE: Symbols in parentheses are not used on these modules but
may be used for other modules in this product family. They
are for reference only.
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.



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PART NUMBERS
FPM Operating Mode
PART NUMBER
MT4LDT464HG-x
MT4LDT464HG-x S
MT8LDT864HG-x
MT8LDT864HG-x S
x = speed
CONFIGURATION
4 Meg x 64
4 Meg x 64
8 Meg x 64
8 Meg x 64
REFRESH
Standard
Self
Standard
Self
EDO Operating Mode
PART NUMBER
MT4LDT464HG-x X
MT4LDT464HG-x XS
MT8LDT864HG-x X
MT8LDT864HG-x XS
x = speed
CONFIGURATION
4 Meg x 64
4 Meg x 64
8 Meg x 64
8 Meg x 64
REFRESH
Standard
Self
Standard
Self
GENERAL DESCRIPTION
The MT4LDT464H (X)(S) and MT8LDT864H (X)(S)
are randomly accessed 32MB and 64MB memories
organized in a small-outline, x64 configuration. They
are specially processed to operate from 3V to 3.6V for
low-voltage memory systems.
During READ or WRITE cycles, each location is
uniquely addressed via the address bits. The row ad-
dress is latched by the RAS# signal, then the column
address is latched by the CAS# signal.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE oc-
curs when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data outputs (Q) will remain
High-Z, regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data outputs prior to apply-
ing input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping OE# LOW, no
WRITE will occur, and the data outputs will drive read
data from the access location.
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data
operations (READ or WRITE) within a row-address-
defined page boundary. The FAST-PAGE-MODE cycle
is always initiated with a row address strobed in by
RAS#, followed by a column address strobed in by
4, 8 MEG x 64
DRAM SODIMMs
CAS#. Additional columns may be accessed by provid-
ing valid column addresses, strobing CAS# and hold-
ing RAS# LOW, thus executing faster memory cycles.
Returning RAS# HIGH terminates the FAST-PAGE-
MODE operation.
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” option,
is an accelerated FAST-PAGE-MODE cycle. The pri-
mary advantage of EDO is the availability of data-out
even after CAS# goes back HIGH. EDO provides for
CAS# precharge time (tCP) to occur without the out-
put data going invalid. This elimination of CAS#
output control provides for pipelined READs.
FAST-PAGE-MODE modules have traditionally
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO operates as any DRAM READ or
FAST-PAGE-MODE READ, except data will be held
valid after CAS# goes HIGH, as long as RAS# and OE#
are held LOW and WE# is held HIGH. (Refer to the 8
Meg x 8 EDO DRAM data sheet for additional infor-
mation on EDO functionality.)
REFRESH
Memory cell data is retained in its correct state by
maintaining power and executing any RAS# cycle
(READ, WRITE) or RAS# refresh cycle (RAS#-ONLY,
CBR or HIDDEN) so that all combinations of RAS#
addresses are executed at least every tREF, regardless of
sequence. The CBR REFRESH cycle will invoke the
internal refresh counter for automatic RAS# address-
ing.
An optional self refresh mode is also available on
the “S” version. The “S” option allows the user the
choice of a fully static, low-power data retention mode
or a dynamic refresh mode at the extended refresh
period of 128ms, or 125µs per row when using distrib-
uted CBR REFESH. The optional self refresh feature is
initiated by performing a CBR REFRESH cycle and
holding RAS# LOW for the specified tRASS.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of tRPS. This delay allows
for the completion of any internal refresh cycles that
may be in process at the time of the RAS# LOW-to-
HIGH transition. If the DRAM controller uses a distrib-
uted refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con-
troller utilizes a RAS#-ONLY or burst refresh sequence,
all 1,240 rows must be refreshed within the average
internal refresh rate, prior to the resumption of normal
operation.
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.



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WE#
OE#
RAS0#
CAS0#
CAS1#
CAS2#
CAS3#
A0-A11
CAS4#
CAS5#
CAS6#
CAS7#
4, 8 MEG x 64
DRAM SODIMMs
FUNCTIONAL BLOCK DIAGRAM
MT4LDT464H (X) (32MB)
DQ0-DQ15
DQ16-DQ31
16 16
DQ0-DQ15
WE#
OE#
U1
RAS#
CASL#
CASH# A0ÐA11
12
DQ0-DQ15
WE#
OE#
U2
RAS#
CASL#
CASH# A0ÐA11
12
DQ32-DQ47
16
DQ0-DQ15
WE#
OE#
U3
RAS#
CASL#
CASH# A0ÐA11
12
DQ48-DQ63
16
DQ0-DQ15
WE#
OE#
U4
RAS#
CASL#
CASH# A0ÐA11
12
SPD
SCL
SA0 SA1 SA2
SDA
U1-U4 = MT4LC4M16R6 EDO PAGE MODE
U1-U4 = MT4LC4M16F5 FAST PAGE MODE
VDD U1-U4
VSS U1-U4
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 – Rev. 2/99
3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.



No Preview Available !

WE#
OE#
RAS0#
CAS0#
CAS1#
CAS2#
CAS3#
A0-A11
CAS4#
CAS5#
CAS6#
CAS7#
DQ0-DQ7
8
DQ0-DQ7
WE#
OE#
U1
RAS#
CAS#
A0ÐA11
12
FUNCTIONAL BLOCK DIAGRAM
MT8LDT864H (X) (64MB)
DQ8-DQ15
8
DQ16-DQ23
8
4, 8 MEG x 64
DRAM SODIMMs
DQ24-DQ31
8
DQ0-DQ7
WE#
OE#
U2
RAS#
CAS#
A0ÐA11
12
DQ0-DQ7
WE#
OE#
U3
RAS#
CAS#
A0ÐA11
12
DQ0-DQ7
WE#
OE#
U4
RAS#
CAS#
A0ÐA11
12
DQ32-DQ39
8
DQ0-DQ7
WE#
OE#
U5
RAS#
CAS#
A0ÐA11
12
DQ40-DQ47
8
DQ0-DQ7
WE#
OE#
U6
RAS#
CAS#
A0ÐA11
12
DQ48-DQ55
8
DQ0-DQ7
WE#
OE#
U7
RAS#
CAS#
A0ÐA11
12
DQ56-DQ63
8
DQ0-DQ7
WE#
OE#
U8
RAS#
CAS#
A0ÐA11
12
SPD
SCL
SA0 SA1 SA2
SDA
VDD
VSS
U1-U8
U1-U8
U1-U8 = MT4LC8M8B6 FAST PAGE MODE
U1-U8 = MT4LC8M8C2 EDO PAGE MODE
4, 8 Meg x 64 DRAM SODIMMs
DM83.p65 Rev. 2/99
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.



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