MT4LC16M4G3 Datasheet PDF - Micron Technology

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MT4LC16M4G3
Micron Technology

Part Number MT4LC16M4G3
Description DRAM
Page 22 Pages


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DRAM
16 MEG x 4
EDO DRAM
MT4LC16M4G3, MT4LC16M4H9
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/mti/msp/html/datasheet.html
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x4 pinout, timing, functions,
and packages
• 12 row, 12 column addresses (H9) or
13 row, 11 column addresses (G3)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compat-
ible
• Extended Data-Out (EDO) PAGE MODE access
• Optional self refresh (S) for low-power data
retention
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
OPTIONS
• Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
MARKING
H9
G3
• Plastic Packages
32-pin SOJ (400 mil)
32-pin TSOP (400 mil)
DJ
TG
• Timing
50ns access
60ns access
-5
-6
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
None
S*
NOTE: 1. The 16 Meg x 4 EDO DRAM base number
differentiates the offerings in one place—
MT4LC16M4H9. The fifth field distinguishes the
address offerings: H9 designates 4K addresses and
G3 designates 8K addresses.
2. The “#” symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC16M4H9DJ-6
KEY TIMING PARAMETERS
SPEED
-5
-6
tRC
84ns
104ns
tRAC
50ns
60ns
tPC
20ns
25ns
tAA
25ns
30ns
tCAC
13ns
15ns
tCAS
8ns
10ns
PIN ASSIGNMENT (Top View)
32-Pin SOJ
32-Pin TSOP
VCC
DQ0
DQ1
NC
NC
NC
NC
WE#
RAS#
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 Vss
31 DQ3
30 DQ2
29 NC
28 NC
27 NC
VCC
DQ0
DQ1
NC
NC
NC
NC
1
2
3
4
5
6
7
26 CAS#
WE# 8
25 OE#
RAS# 9
24 NC/A12** A0 10
23 A11
A1 11
22 A10
A2 12
A3 13
21 A9
A4 14
20 A8
A5 15
19 A7
VCC 16
18 A6
17 Vss
**NC on H9 version, A12 on G3 version
32 Vss
31 DQ3
30 DQ2
29 NC
28 NC
27 NC
26 CAS#
25 OE#
24 NC/A12**
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 Vss
16 MEG x 4 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC16M4H9DJ-x
MT4LC16M4H9DJ-x S
MT4LC16M4H9TG-x
MT4LC16M4H9TG-x S
MT4LC16M4G3DJ-x
MT4LC16M4G3DJ-x S
MT4LC16M4G3TG-x
MT4LC16M4G3TG-x S
x = speed
REFRESH
ADDRESSING
4K
4K
4K
4K
8K
8K
8K
8K
PACKAGE
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
REFRESH
Standard
Self
Standard
Self
Standard
Self
Standard
Self
GENERAL DESCRIPTION
The 16 Meg x 4 DRAM is a high-speed CMOS,
dynamic random-access memory device containing
67,108,864 bits and designed to operate from 3V to
3.6V. The MT4LC16M4H9 and MT4LC16M4G3 are
functionally organized as 16,777,216 locations con-
taining 4 bits each. The 16,777,216 memory locations
are arranged in 4,096 rows by 4,096 columns on the H9
version and 8,192 rows by 2,048 columns on the G3
version. During READ or WRITE cycles, each location is
16 Meg x 4 EDO DRAM
D22_2.p65 – Rev. 5/00
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.



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WE#
CAS#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RAS#
WE#
CAS#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
RAS#
16 MEG x 4
EDO DRAM
NO. 2 CLOCK
GENERATOR
FUNCTIONAL BLOCK DIAGRAM
MT4LC16M4G3 (13 row addresses)
CONTROL
LOGIC
DATA-IN
BUFFER
DATA-OUT
BUFFER
4
4
4
COLUMN-
11
ADDRESS
BUFFER(11)
REFRESH
CONTROLLER
REFRESH
COUNTER
13
ROW-
13 ADDRESS
BUFFERS (13)
13
11
8,192
8,192
COLUMN
DECODER
2,048
4
SENSE AMPLIFIERS
I/O GATING
2,048
8,192 x 2,048 x 4
MEMORY
ARRAY
DQ0
DQ1
DQ2
DQ3
OE#
NO. 1 CLOCK
GENERATOR
NO. 2 CLOCK
GENERATOR
COLUMN-
12
ADDRESS
BUFFER(12)
REFRESH
CONTROLLER
REFRESH
COUNTER
12
ROW-
12 ADDRESS
BUFFERS (12)
FUNCTIONAL BLOCK DIAGRAM
MT4LC16M4H9 (12 row addresses)
VDD
VSS
CONTROL
LOGIC
DATA-IN
BUFFER
DATA-OUT
BUFFER
4
4
4
DQ0
DQ1
DQ2
DQ3
OE#
12
COLUMN
DECODER
4,096
4
SENSE AMPLIFIERS
I/O GATING
4,096
4,096 x 4,096 x 4
MEMORY
12
4,096
4,096
ARRAY
NO. 1 CLOCK
GENERATOR
VDD
VSS
16 Meg x 4 EDO DRAM
D22_2.p65 – Rev. 5/00
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.



No Preview Available !

16 MEG x 4
EDO DRAM
GENERAL DESCRIPTION (Continued)
uniquely addressed via the address bits. First, the row
address is latched by the RAS# signal, then the column
address is latched by CAS#. The device provides EDO-
PAGE-MODE operation, allowing for fast successive
data operations (READ, WRITE, or READ-MODIFY-
WRITE) within a given row.
The 16 Meg x 4 DRAM must be refreshed periodically
in order to retain stored data.
DRAM ACCESS
Each location in the DRAM is uniquely addressable,
as mentioned in the General Description. The data for
each location is accessed via the four I/O pins (DQ0-
DQ3). A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE occurs
when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data outputs (Q) will remain
High-Z, regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data outputs prior to apply-
ing input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping OE# LOW, no WRITE
will occur, and the data outputs will drive read data
from the accessed location.
EDO PAGE MODE
DRAM READ cycles have traditionally turned the
output buffers off (High-Z) with the rising edge of
CAS#. If CAS# went HIGH and OE# was LOW (active),
the output buffers would be disabled. The 16 Meg x 4
DRAM offers an accelerated page mode cycle by elimi-
nating output disable from CAS# HIGH. This option is
called EDO and it allows CAS# precharge time (tCP) to
occur without the output data going invalid (see READ
and EDO-PAGE-MODE READ waveforms).
EDO operates like any DRAM READ or FAST-PAGE-
MODE READ, except data is held valid after CAS# goes
HIGH, as long as RAS# and OE# are held LOW and WE#
is held HIGH. OE# can be brought LOW or HIGH while
CAS# and RAS# are LOW, and the DQs will transition
between valid data and High-Z. Using OE#, there are
two methods to disable the outputs and keep them
disabled during the CAS# HIGH time. The first method
is to have OE# HIGH when CAS# transitions HIGH and
keep OE# HIGH for tOEHC thereafter. This will disable
the DQs, and they will remain disabled (regardless of
the state of OE# after that point) until CAS# falls again.
The second method is to have OE# LOW when CAS#
transitions HIGH and then bring OE# HIGH for a
minimum of tOEP anytime during the CAS# HIGH
period. This will disable the DQs, and they will remain
disabled (regardless of the state of OE# after that point)
until CAS# falls again. (Please refer to Figure 1.) During
other cycles, the outputs are disabled at tOFF time after
RAS# and CAS# are HIGH or at tWHZ after WE# transi-
tions LOW. The tOFF time is referenced from the rising
edge of RAS# or CAS#, whichever occurs last. WE# can
also perform the function of disabling the output
drivers under certain conditions, as shown in Figure 2.
EDO-PAGE-MODE operations are always initiated
with a row address strobed in by the RAS# signal,
followed by a column address strobed in by CAS#, just
like for single location accesses. However, subsequent
column locations within the row may then be accessed
at the page mode cycle time. This is accomplished by
cycling CAS# while holding RAS# LOW and entering
new column addresses with each CAS# cycle. Returning
RAS# HIGH terminates the EDO-PAGE-MODE opera-
tion.
DRAM REFRESH
The supply voltage must be maintained at the speci-
fied levels, and the refresh requirements must be met in
order to retain stored data in the DRAM. The refresh
requirements are met by refreshing all 8,192 rows (G3)
or all 4,096 rows (H9) in the DRAM array at least once
every 64ms. The recommended procedure is to execute
4,096 CBR REFRESH cycles, either uniformly spaced or
grouped in bursts, every 64ms. The MT4LC16M4G3
internally refreshes two rows for every CBR cycle,
whereas the MT4LC16M4H9 refreshes one row for
every CBR cycle. So with either device, executing 4,096
CBR cycles covers all rows. The CBR refresh will invoke
the internal refresh counter for automatic RAS# ad-
dressing. Alternatively, RAS#-ONLY REFRESH capabil-
ity is inherently provided. However, with this method,
some compatibility issues may become apparent. For
example, both G3 and H9 versions require 4,096 CBR
REFRESH cycles, yet each requires a different number of
RAS#-ONLY REFRESH cycles (G3 = 8,192 and H9 =
4,096). JEDEC strongly recommends the use of CBR
REFRESH for this device.
An optional self refresh mode is also available on the
“S” version. The self refresh feature is initiated by
performing a CBR REFRESH cycle and holding RAS#
LOW for the specified tRASS. The “S” option allows for
an extended refresh period of 128ms, or 31.25µs per
row for a 4K refresh and 15.625µs per row for an 8K
refresh, when using a distributed CBR REFRESH. This
refresh rate can be applied during normal operation, as
well as during a standby or battery backup mode.
16 Meg x 4 EDO DRAM
D22_2.p65 – Rev. 5/00
3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.



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DRAM REFRESH (Continued)
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of tRPS. This delay allows for
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con-
troller uses RAS#-ONLY or burst CBR refresh, all rows
RAS# VVIIHL
16 MEG x 4
EDO DRAM
must be refreshed with a refresh rate of tRC minimum
prior to resuming normal operation.
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ VVIIOOHL
OE#
V
V
IH
IL
RAS#
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR VVIIHL
OPEN
VALID DATA (A)
tOD
tOES
tOE
VALID DATA (A)
VALID DATA (B)
tOD
tOEHC
VALID DATA (C)
tOD
tOEP
VALID DATA (D)
The DQs go back to
Low-Z if tOES is met.
The DQs remain High-Z
until the next CAS# cycle
if tOEHC is met.
Figure 1
OE# Control of DQs
The DQs remain High-Z
until the next CAS# cycle
if tOEP is met.
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
DQ
V
V
IOH
IOL
WE# VVIIHL
OE# VVIIHL
OPEN
VALID DATA (A)
tWHZ
tWPZ
VALID DATA (B)
tWHZ
INPUT DATA (C)
The DQs go to High-Z if WE# falls and, if tWPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
Figure 2
WE# Control of DQs
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
DON’T CARE
UNDEFINED
16 Meg x 4 EDO DRAM
D22_2.p65 – Rev. 5/00
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.



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