MR27V6466F Datasheet PDF - OKI electronic

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MR27V6466F
OKI electronic

Part Number MR27V6466F
Description Synchronous One Time PROM
Page 30 Pages


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PEDR27V6466F-01-08
1Semiconductor
MR27V6466F
This version: Jul. 2001
Previous version: Jun. 2001
Preliminary
4,194,304-Word x 16-Bit or 2,097,152-Word x 32-Bit Synchronous One Time PROM
GENERAL DESCRIPTION
The MR27V6466F is a 64 Mbit One Time Programmable Synchronous Read Only Memory whose configuration
can be electrically switched between 4,194,304 x 16 bit (word mode) and 2,097,152 x 32 bit (double word mode)
by the state of the WORD pin. The MR27V6466F supports high speed synchronous read operation using a single
3.3 V power supply.
FEATURES ON READ
• 3.3 V power supply
• LVTTL compatible with multiplexed address
• Dual electrically switchable configuration
4M x 16 (word mode) / 2M x 32 (double word mode)
• All inputs are sampled at the rising edge of the system clock.
• High speed read operation
100 MHz : CAS Latency = 5, 6 tRCD min: 2 clock cycles
66 MHz : CAS Latency = 5, 6 tRCD min: 2 clock cycles
50 MHz : CAS Latency = 4, 5, 6 tRCD min: 1 clock cycles
Burst length (4, 8)
Data scramble (sequential, interleave)
• DQM for data out masking
• No Precharge operation is required. No Refresh operation is required.
• No power on sequence is required.
Mode register is automatically initialized to the default state after power on.
“Row Active” or “Mode Register Set” command is applicable as the first command just after power on.
• Single Bank operation
• Package: TSOP(2)86-P-400-0.50-K (Product Name : MR27V6466FTA)
FEATURES ON PROGRAMMING
• 8.0 V programming power supply
• Programming algorithm is compatible with conventional asynchronous OTP.
MR27V6466F can be programmed with conventional EPROM programmers.
Synchronous Burst read or Static Programming Operation is selected by the state of STO pin.
High STO level enables full static programming. (Program, Program Verify, Asynchronous Read)
Low STO level enables synchronous burst read.
Exclusive 86-pin socket adapters are available from OKI to support programming requirements.
The socket adapter is used on a 48-DIP socket on the programmer.
The socket adapter for 64M synchronous OTP is distinguished from the socket adapter for 32M SOTP.
The socket adapter is designed with the STO pin connected to VCC in order to program MR27V6466F as
conventional OTP.
EPROM programmer must have the algorithm for MR27V6466F on the exclusive socket adapter.
*Device damage can occur if improper algorithm is used.
• Programming with address multiplexed input is also available.
• High speed programming
25 µs programming pulse per word allows high speed programming.
1/39
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1Semiconductor
BLOCK DIAGRAM
PEDR27V6466F-01-08
MR27V6466F
A0
|
A12
CS
RAS
CAS
MR
WORD
Command
Controller
Mode
Register
Burst sequence
Controller
Memory Cell Array
2 M x 32 or 4 M x 16
Column Select
Sense Amplifier
& Program Bias
Data Output
Latch
Data Input
Buffer
Data Output
Selector
CLK Buffer
Program Mode
Controller
Data Output / Input Buffer
& Data Output / Address Buffer
CKE CLK
OE STO DQ23 to DQ31
CE
AMPX
CAP0 to CAP8
DQ0 to DQ15
DQ16 to DQ22
2/39
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1Semiconductor
PEDR27V6466F-01-08
MR27V6466F
PIN CONFIGURATION
VCC
DQ0
VCCQ
DC
DQ1
VSSQ
DC
DQ2
VCCQ
DC
DQ3
VSSQ
DC
DC
VCC
DC
NC
CAS
RAS
DC
WORD
A12
A11
A10
A0
A1
A2
NC
VCC
NC
DQ4
VSSQ
DC
DQ5
VCCQ
DC
DQ6
VSSQ
DC
DQ7
VCCQ
CAP8
VCC
TOP VIEW
Programming in Static Operation (STO is high)
Synchronous Read (STO is VSS or open)
VCC
DQ0
VCCQ
DQ16
DQ1
VSSQ
DQ17
DQ2
VCCQ
DQ18
DQ3
VSSQ
DQ19
MR
VCC
DQM
NC
CAS
RAS
CS
WORD
A12
A11
A10
A0
A1
A2
NC
VCC
NC
DQ4
VSSQ
DQ20
DQ5
VCCQ
DQ21
DQ6
VSSQ
DQ22
DQ7
VCCQ
DQ23
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86 VSS
85 DQ31
84 VSSQ
83 DQ15
82 DQ30
81 VCCQ
80 DQ14
79 DQ29
78 VSSQ
77 DQ13
76 DQ28
75 VCCQ
74 DQ12
73 NC
72 VSS
71 DC
70 DC
69 DC
68 CLK
67 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DC
58 VSS
57 DC
56 DQ27
55 VCCQ
54 DQ11
53 DQ26
52 VSSQ
51 DQ10
50 DQ25
49 VCCQ
48 DQ9
47 DQ24
46 VSSQ
45 DQ8
44 VSS
VSS
CAP0
VSSQ
DQ15
CAP1
VCCQ
DQ14
CAP2
VSSQ
DQ13
CAP3
VCCQ
DQ12
NC
VSS
VPP
CE
OE
DC
DC
A9
A8
A7
A6
A5
A4
A3
AMPX
VSS
STO
CAP4
VCCQ
DQ11
CAP5
VSSQ
DQ10
CAP6
VCCQ
DQ9
CAP7
VSSQ
DQ8
VSS
DC (Don’t Care) : Logical input level is ignored. However the pin is connected to the input
buffer of OTP.
3/39
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1Semiconductor
PEDR27V6466F-01-08
MR27V6466F
PIN FUNCTION FOR SYNCHRONOUS READ OPERATION
(STO pin is low level or open)
Pin Name
STO
CLK
CS
CKE
A0 to A12
RAS
CAS
MR
DQ0 to DQ31
DQM
WORD
VCC
VSS
VCCQ
VSSQ
NC
DC
Function
Static Operation
System Clock
Chip Select
Clock Enable
Address
Row Address Strobe
Column Address Strobe
Mode Register Set
Data Output
Data Output Masking
x32/x16 Organization Selection
Power Supply
Ground
Data Output Power Supply
Data Output Ground
No Connection
Don't Care
Description
Must be low for synchronous operation. Internal resistance
(around 10k ohms) pulls the input level down to VSS when this
pin is open. High level STO enables programming operation
compatible with standard OTPs.
All inputs are sampled at the rising edge.
Enables command sampling by the CLK signal with a low level
on the CS input.
Masks internal system clock to freeze the CLK operation of
subsequent CLK cycle. CKE must be enabled for command
sampling cycles. CLK is disabled for two types of operations.
1) Clock Suspend
2) Power Down
Row and column addresses are multiplexed on the same pins.
Row address: RA0 to RA12
Column address: CA0 to CA7 (x32) /CA0 to CA8 (x16)
LSB:CA0(Both x32 and x16)
Functionality depends on the combination.
See the function table.
Data outputs are valid at the rising edge of CLK for read
cycles. Except for read cycles DQn is high-Z state.
Data outputs are masked after two cycles from when high level
DQM is applied.
The WORD pin defines the organization of each read
command to be x16 (word mode) or x32 (double word mode).
High = x32
Low = x16
When WORD is low (x16,word mode) ,DQ16 to DQ31 are
held on High-Z state.
3.3 V Power supply
3.3 V Power supply to DQ0-DQ31
Logical input level is ignored.
4/39
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