MPS6551 Datasheet PDF - Commodore

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MPS6551
Commodore

Part Number MPS6551
Description ASYNCHRONOUS COMMUNICATION INTERFACE ADAPTER
Page 8 Pages


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, . .commodore
~ aamiconduct:ar group
~~@~
MPS
6551
ASSYNCH RONOUS
COMMUNICATION
INTERFACE
ADAPTER
[ 6551 ASYNCHRONOUS COMMUNICATION INTERFACE ADAPTER
CONCEPT:
The 6551 is an Asynchronous Communication Adapter (ACIA) intended to provide for interfacing the 6500/6800
microprocessor families to serial communication data sets and modems. A unique feature is the inclusion of an
on-chip programmable baud rate generator, with a crystal being the only external com pone t required.
FEATURES:
• On-chip baud rate generator: 15 programmable baud
rates derived from a standard 1.8432 M Hz external
crystal (50 to 19,200 baud).
• Programmable interrupt and status register to simplify
software design.
• Single +5 volt power supply.
• Serial echo mode.
• False start bit detection.
• 8-bit bi-directional data bus for direct communicati~
)
-standard baud rates (up
engths; number of stop bits; and
nd detection.
control signals provided.
:¥ep';' none, mark, space).
r half-duplex operation.
9 bit transmission.
ORDER NUMBER
MXS 6551
PACKAGE DESIGNATOR
C = CERAMIC
P = PLASTIC
6551 PIN CONFIGURATION
GND 1
2
3
4
5
6
7
RTS 8
CTS 9
TxD 10
l5'i'R 11
RxD 12
RSO 13
RS1 14
28 R/W
27 ~2
26 iRa
25 DB7
24 DB6
23 DB5
22 DB4
21 DB3
20 DB2
19 DB1
18 DBO
17 DSR
16 DCD
15 Vce
2-129



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Figure 1. Block Diagram
MPS
6551
132
R;W
CSo
CS1
RSO
RS1
RES
SELECT
AND
CONTROL
LOGIC
DATA
BUS
BUFFERS
TRANSMIT
CONTROL
CTS
TRANSMIT
DATA
REGISTER
STATUS
REGISTER
CONTROL
REGISTER
RECEIVE
DATA
REGISTER
TRANSMIT
SHIFT
REGISTER
TxD
INTERRUPT
LOGIC
fRO
OCD
i5SR
BAUD
RATE
GENERATOR
RxC
XTAL 1
XTAL2
RECEIVE
SHIFT
REGISTER
RxD
COMMAND
REGISTER
RECEIVE
CONTROL
L------------__ DiR
L-------------__________~_Rf:S
2-130



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MPS
6551
MAXIMUM RATINGS
Supply Voltage, Vcc
Input/Output Voltage, VIN
Operating Temperature, TOp
Storage Temperature, TSTG
-0.3V to +7.0V
-0.3V to +7.0V
ODC to 70DC
-55DC to 150°C
All inputs contain protection circuitry to prevent damage due
to high static discharges. Care should be exercised to
prevent unnecessary application of voltages in excess of the
allowable limits.
COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
Implied and exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS \Vee = 5.aV + 5%, TA = a to 7aoe, unless otherwise noted)
r-----------------------------.-----.----.---~---,_----~
Characteristic
Symbol Min Typ Max Unit
Input High Voltage
2.0 VCC v
Input Low Voltage
-0.3
0.8 V
Input LeaJs,.age Cu~nt: VI N=O to 5V. _
__
(t/},~R!W, RES, CSO, CS1, RSO, RS1, CTS, RxD, DCD,
DSR)
±1.0
±2.5
IJA
r--------------------------+-----~--~----~----~-------.-
Input Leakage Current for High Impedance State
(Three State)
ITSI
±2.0 ±10.0
IJA
Output High Voltage: ILOAD=-1 OO,uA
Output Low Voltage: ILOAD = 1.6mA
(DBO-DB7, TxD, RxC, RTS, DTR, IRO)
VOH
VOL
204
V
0.4 V
Output High Current (Sourcing): VOH=2.4V
Output Low Current (Sinking): VOL=Oo4V
Output Leakage Current (off state): VOUT=5V
(IRQ)
10H -250
10L. 1.6
10FF
1.0 10.0
Clock Capacitance (02)
Input Capacitance (except XTAL1 and XTAL2)
CCLK
20 pF
10 pF
Output Capacitance
Power Dissipation
COUT
Po
10 pF
170 300 mw
I
Power Dissipation vs Temperature
200
TYPICAL
POWER
DISSIPATION
(mWI
1711
~
~150
126
-~
100o
20 40 10
T"-ENT I"CI
III
2-131



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MPS
6551
XTAL 1
(TRANSMIT
CLOCK INPUT)
TxO
NOTE: TxO rate is 1/16 TxC rate.
Figure 48. Transmit Timing with External Clock
RxC
(INPUT)
OTR
IRQ
(CLEAR) _ _ _ _ _ _ _ _ _ _.....J
Figure 4b. Interrupt and RTS Timing
NOTE: RxO rate is 1/16 RxC rate.
Figure 4c. Receive External Clock Timing
TRANSMIT/RECEIVE CHARACTERISTICS
Characteristic
Symbol
6551
Min Max
TransmiVReceive Clock Rate
TransmiVReceive Clock High Time
tCCY
tCH
400*
175
-
-
TransmiVReceive Clock low Time
tCl 175
-
XTAl1 to TxD Propagation Delay
RTS Propagation Delay
-
IRO Propagation Delay (Clear)
a(tr, tf = 1 to 30 nsec)
*The baud rate with external clocking is:
tDD
tRTS
tiRO
Baud Rate =
- 500
- 500
- 500
16xTCCY
6551A
Min Max
400*
-
175 -
175 -
- 500
- 500
- 500
Unit
ns
ns
ns
ns
ns
ns
INTERFACE SIGNAL DESCRIPTION
RES (Reset)
During system initialization a low on the RES input will
cause internal registers to be cleared.
_2 (Input Clock)
The input clock is the system 912 clock and is used to trigger
all data transfers between the system microprocessor and
the 6551.
Rfii (Read/Wrlte)
The RNI is generated by the microprocessor and is used to
control the direction of data transfers. A high on the RNI pin
allows the processor to read the data supplied by the 6551.
A low on the RNI pin allows a write to the 6551.
IRQ (Interrupt Request)
The IRO pin is an interrupt signal from the interrupt control
logic. It is an open drain output, permitting several devices
to be connected to the common IRO microprocessor
input. Normally a high level, IRO goes low when an
interrupt occurs.
DBo - DB7(Data Bus)
The DBO-DB7 pins are the eight data lines used for transfer
of data between the processor and the 6551. These lines
are bi-directional and are normally high-impedance except
during Read cycles when selected.
CSQ, CS1 (Chip Selects)
The two chip select inputs are normally connected to the
processor address lines either directly or through de-
coders. The 6551 is selected when CSO is high and CS1 is
low.
2-132



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