MG2040 Datasheet PDF - ON Semiconductor

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MG2040
ON Semiconductor

Part Number MG2040
Description ESD Protection Diodes
Page 8 Pages


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MG2040, SZMG2040
ESD Protection Diodes
Low Capacitance ESD Protection for
High Speed Video Interface
The MG2040 ESD protection diode is designed specifically to
protect HDMI and Display Port with full functionality ESD protection
and back drive current protection for VCC line. Ultra−low capacitance
and low ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flow−through
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance for the high speed TMDS
lines.
Features
Full Function HDMI / Display Port Solution
Single Connect, Flow through Routing for TMDS Lines
Low Capacitance (0.35 pF Typical, I/O to GND)
Protection for the Following IEC Standards:
IEC 61000−4−2 Level 4 (±8 kV Contact)
UL Flammability Rating of 94 V−0
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
This is a Pb−Free Device
Typical Applications
HDMI
Display Port
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MARKING
DIAGRAM
18 UDFN18
CASE 517CP
1
2040MG
G
2040 = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping
MG2040MUTAG
UDFN18 3000 / Tape &
(Pb−Free)
Reel
SZMG2040MUTAG UDFN18 3000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range TJ −55 to +125 °C
Storage Temperature Range
Tstg − 55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
TL 260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15 kV
±15 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 4
1
Publication Order Number:
MG2040/D



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MG2040, SZMG2040
Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 15 Pin 17
Center Pins, Pin 12, 14, 16, 18
Note: Common GND – Only Minimum of 1 GND connection required
=
Figure 1. Pin Schematic
I/O 1
I/O 2
I/O 3
18 GND
GND 17 I/O
I/O 4
I/O 5
16 GND
I/O 6
GND 15 I/O
I/O 7
I/O 8
I/O 9
14 GND
GND
13 I/O
I/O 10
I/O 11
12 GND
Figure 2. Pin Configuration
Note: Pins 12, 14, 16, 18 and center pins are connected internally as a common ground.
Only minimum of one pin needs to be connected to ground for functionality of all pins.
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MG2040, SZMG2040
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Symbol
Conditions
Min Typ Max
Reverse Working Voltage
VRWM I/O Pin to GND (Note 1)
5.0
Breakdown Voltage
VBR IT = 1 mA, I/O Pin to GND
5.5
Reverse Leakage Current
IR VRWM = 5 V, I/O Pin to GND
1.0
Clamping Voltage (Note 1)
VC IPP = 1 A, I/O Pin to GND (8 x 20 ms pulse)
10
Clamping Voltage (Note 2)
VC IEC61000−4−2, ±8 kV Contact
See Figures 3 and 4
Clamping Voltage
TLP (Note 3)
See Figures 8 through 11
VC IPP = 8 A
IPP = 16 A
IPP = −8 A
IPP = −16 A
11.4
15.3
−4.6
−8.1
Junction Capacitance
CJ VR = 0 V, f = 1 MHz between I/O Pins
0.15 0.20
VR = 0 V, f = 1 MHz between I/O Pins and GND
0.35 0.42
Junction Capacitance
Difference
DCJ VR = 0 V, f = 1 MHz between I/O Pins
VR = 0 V, f = 1 MHz between I/O Pins and GND
0.02
0.04
1. Surge current waveform per Figure 7.
2. For test procedure see Figures 5 and 6 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
Unit
V
V
mA
V
V
pF
pF
90
80
70
60
50
40
30
20
10
0
−10
−20
0 20 40 60 80 100 120
TIME (ns)
Figure 3. IEC61000−4−2 +8 KV Contact
Clamping Voltage
140
0
−10
−20
−30
−40
−50
−20
0 20 40 60 80 100 120 140
TIME (ns)
Figure 4. IEC61000−4−2 −8 KV Contact
Clamping Voltage
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MG2040, SZMG2040
IEC 61000−4−2 Spec.
Level
First Peak
Test Volt- Current Current at
age (kV)
(A) 30 ns (A)
1 2 7.5 4
2 4 15 8
3 6 22.5 12
48
30 16
Current at
60 ns (A)
2
4
6
8
IEC61000−4−2 Waveform
Ipeak
100%
90%
I @ 30 ns
I @ 60 ns
10%
Figure 5. IEC61000−4−2 Spec
tP = 0.7 ns to 1 ns
ESD Gun
TVS
Oscilloscope
50 W
Cable
50 W
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
100
tr
90
80
70
60
50
40
30
20
10
0
0
PEAK VALUE IRSM @ 8 ms
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE IRSM/2 @ 20 ms
tP
20 40
60
t, TIME (ms)
Figure 7. 8 X 20 ms Pulse Waveform
80
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