MC74VHC1GT125 Datasheet PDF - ON Semiconductor

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MC74VHC1GT125
ON Semiconductor

Part Number MC74VHC1GT125
Description Noninverting Buffer / CMOS Logic Level Shifter
Page 8 Pages


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MC74VHC1GT125
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHC1GT125 is a single gate noninverting buffer fabricated
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The MC74VHC1GT125 requires the 3−state control input (OE) to be
set High to place the output into the high impedance state.
The device input is compatible with TTL−type input thresholds and the
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT125 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT125 to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when VCC = 0 V.
These input and output structures help prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 62; Equivalent Gates = 16
OE 1
IN A 2
GND 3
5 VCC
4 OUT Y
Figure 1. Pinout (Top View)
OE
IN A OUT Y
Figure 2. Logic Symbol
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MARKING
DIAGRAMS
SC−88A / SOT−353/SC−70
DF SUFFIX
CASE 419A
W1d
Pin 1
d = Date Code
TSOP−5/SOT−23/SC−59
DT SUFFIX
CASE 483
W1d
Pin 1
d = Date Code
PIN ASSIGNMENT
1 OE
2 IN A
3 GND
4 OUT Y
5 VCC
FUNCTION TABLE
A Input
OE Input
Y Output
LL
HL
XH
L
H
Z
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2003
December, 2003 − Rev. 8
1
Publication Order Number:
MC74VHC1GT125/D



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MC74VHC1GT125
MAXIMUM RATINGS (Note 1)
Symbol
Characteristics
Value
Unit
VCC
VIN
VOUT
IIK
IOK
IOUT
ICC
PD
qJA
TL
TJ
Tstg
VESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
DC Supply Current, VCC and GND
Power Dissipation in Still Air
Thermal Resistance
Lead Temperature, 1 mm from Case for 10 s
Junction Temperature Under Bias
Storage Temperature
ESD Withstand Voltage
VCC = 0
High or Low State
VOUT < GND; VOUT > VCC
SC−88A, TSOP−5
SC−88A, TSOP−5
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
−0.5 to +7.0
−0.5 to +7.0
−0.5 to 7.0
−0.5 to VCC + 0.5
−20
+20
+25
+50
200
333
260
+150
−65 to +150
> 2000
> 200
N/A
V
V
V
mA
mA
mA
mA
mW
°C/W
°C
°C
°C
V
ILatch−Up Latch−Up Performance
Above VCC and Below GND at 125°C (Note 5)
±500
mA
1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute−maximum−rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
2. Tested to EIA/JESD22−A114−A
3. Tested to EIA/JESD22−A115−A
4. Tested to JESD22−C101−A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
VCC
VIN
VOUT
TA
tr , tf
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature Range
Input Rise and Fall Time
VCC = 5.0 V ± 0.5 V
Min
3.0
0.0
0.0
−55
0
Max
5.5
5.5
VCC
+125
20
Unit
V
V
V
°C
ns/V
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature 5C
80
90
100
110
120
130
140
Time, Hours
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
Time, Years
117.8
47.9
20.4
9.4
4.2
2.0
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
1
1 10
100 1000
TIME, YEARS
Figure 3. Failure Rate vs. Time
Junction Temperature
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MC74VHC1GT125
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIH
Parameter
Minimum High−Level
Input Voltage
Test Conditions
VCC
TA = 25°C
TA 85°C −55 TA 125°C
(V) Min Typ Max Min Max Min
Max Unit
3.0 1.4
4.5 2.0
5.5 2.0
1.4 1.4
2.0 2.0
2.0 2.0
V
VIL Maximum Low−Level
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage
3.0
0.53 0.53
0.53 V
4.5
0.8 0.8
0.8
5.5
0.8 0.8
0.8
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIIN
Minimum High−Level
Output Voltage
VIN = VIH or VIL
Maximum Low−Level
Output Voltage
VIN = VIH or VIL
Maximum Input
Leakage Current
VIN = VIH or VIL
IOH = − 50 mA
VIN = VIH or VIL
IOH = − 4 mA
IOH = − 8 mA
VIN = VIH or VIL
IOL = 50 mA
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
VIN = 5.5 V or GND
3.0 2.9 3.0 2.9 2.9
4.5 4.4 4.5 4.4 4.4
V
3.0 2.58
4.5 3.94
2.48 2.34
3.80 3.66
3.0 0.0 0.1 0.1
4.5 0.0 0.1 0.1
0.1 V
0.1
3.0
0.36 0.44
0.52
4.5
0.36 0.44
0.52
0 to
± 0.10
± 1.0
± 1.0 mA
5.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
Maximum Quiescent
VIN = VCC or GND
Supply Current
5.5
1.0 20
40 mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICCT
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIOPD
Quiescent Supply
Current
Output Leakage
Current
Input: VIN = 3.4 V
Other Input: VCC or GND
VOUT = 5.5 V
5.5
0.0
1.35 1.50
0.5 5.0
1.65 mA
10 mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIOZ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIOPD
Maximum 3−State
Leakage Current
Output Leakage
Current
VIN = VIH or VIL
VOUT = VCC or GND
VOUT = 5.5 V
5.5
0.0
± 0.25
0.5
± 2.5
5.0
± 2.5 mA
10 mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS Inputtr=tf=3.0ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Parameter
Maximum Propagation
Delay, A to Y
(Figures 3. and 5.)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPZL,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPZH
Maximum Output
Enable TIme,OE to Y
(Figures 4. and 5.)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLZ,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHZ
Maximum Output
Disable Time,OE to Y
(Figures 4. and 5.)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCin MaximumInputCapacitance
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCout MaximumThree−State
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Capacitance (Output
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎin High Impedance State)
Test Conditions
VCC = 3.3 ± 0.3 V CL = 15pF
CL = 50pF
VCC = 5.0 ± 0.5 V CL = 15pF
CL = 50pF
VCC = 3.3 ± 0.3 V CL = 15pF
RL = RI = 500 W CL = 50pF
VCC = 5.0 ± 0.5 V CL = 15pF
RL = RI = 500 W CL = 50pF
VCC = 3.3 ± 0.3 V CL = 15pF
RL = RI = 500 W CL = 50pF
VCC = 5.0 ± 0.5 V CL = 15pF
RL = RI = 500 W CL = 50pF
TA = 25°C
Min Typ Max
5.6 8.0
8.1 11.5
3.8 5.5
5.3 7.5
5.4 8.0
7.9 11.5
3.6 5.1
5.1 7.1
6.5 9.7
8.0 13.2
4.8 6.8
7.0 8.8
4 10
6
TA 85°C
Min Max
1.0 9.5
1.0 13.0
1.0 6.5
1.0 8.5
1.0 9.5
1.0 13.0
1.0 6.0
1.0 8.0
1.0 11.5
1.0 15.0
1.0 8.0
1.0 10.0
10
−55 TA 125°C
Min Max Unit
12.0 ns
16.0
8.5
10.5
11.5 ns
15.0
7.5
9.5
14.5 ns
18.0
10.0
12.0
10 pF
pF
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Note 6)
14 pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 4 (per buffer). CPD is used to determine the
no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.
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MC74VHC1GT125
SWITCHING WAVEFORMS
A
tPLH
50%
50% VCC
Y
VCC
GND
tPHL
Figure 4. Switching Waveforms
OE 50%
tPZL tPLZ
Y 50% VCC
tPZH tPHZ
Y 50% VCC
Figure 5.
VCC
GND
HIGH
IMPEDANCE
VOL + 0.3V
VOH − 0.3V
HIGH
IMPEDANCE
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
DEVICE
UNDER
TEST
TEST POINT
OUTPUT 1 kW
CL *
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 6. Test Circuit
*Includes all probe and jig capacitance
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
DEVICE ORDERING INFORMATION
Device Nomenclature
Device
Order Number
Temp
Circuit Range
Device Package
Indicator Identifier Technology Function Suffix
Tape &
Reel
Suffix
Package Type
(Name/SOT#/
Common Name)
Tape and
Reel Size
MC74VHC1GT125DF1 MC
74
VHC1G
T125
DF
SC−88A / SOT−353 178 mm (7”)
1
/ SC−70
3000 Unit
MC74VHC1GT125DF2 MC
74
VHC1G
T125
DF
SC−88A / SOT−353 178 mm (7”)
2
/ SC−70
3000 Unit
MC74VHC1GT125DT1 MC
74
VHC1G
T125
DT
TSOPS / SOT−23 178 mm (7”)
1
/ SC−59
3000 Unit
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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