MC74HC374A Datasheet PDF - ON Semiconductor

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MC74HC374A
ON Semiconductor

Part Number MC74HC374A
Description Octal 3-State Non-Inverting D Flip-Flop
Page 8 Pages


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MC74HC374A
Octal 3-State Non-Inverting
D Flip-Flop
High–Performance Silicon–Gate CMOS
The MC74HC374A is identical in pinout to the LS374. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the clock. The Output Enable input does not affect the states of
the flip–flops, but when Output Enable is high, the outputs are forced
to the high–impedance state; thus, data may be stored even when the
outputs are not enabled.
The HC374A is identical in function to the HC574A which has the
input pins on the opposite side of the package from the output. This
device is similar in function to the HC534A which has inverting
outputs.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 266 FETs or 66.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0 3
D1 4
D2 7
D3 8
D4 13
D5 14
D6 17
D7 18
CLOCK 11
2 Q0
5 Q1
6 Q2
9 Q3
12 Q4
15 Q5
16 Q6
19 Q7
NONINVERTING
OUTPUTS
OUTPUT ENABLE 1
FUNCTION TABLE
PIN 20 = VCC
PIN 10 = GND
Output
Enable
L
L
L
H
Inputs
Clock
L,H,
X
Output
DQ
HH
LL
X No Change
XZ
X = don’t care
Z = high impedance
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20
1
20
1
PDIP–20
N SUFFIX
CASE 738
SOIC WIDE–20
DW SUFFIX
CASE 751D
MARKING
DIAGRAMS
20
MC74HC374AN
AWLYYWW
1
20
HC374A
AWLYYWW
1 20
20
1
TSSOP–20
DT SUFFIX
CASE 948G
HC
374A
ALYW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
1
2
20 VCC
19 Q7
D0 3
18 D7
D1 4
17 D6
Q1 5
16 Q6
Q2 6
15 Q5
D2 7
14 D5
D3 8
13 D4
Q3 9
12 Q4
GND 10
11 CLOCK
ORDERING INFORMATION
Device
Package Shipping
MC74HC374AN
PDIP–20 1440 / Box
MC74HC374ADW
SOIC–WIDE 38 / Rail
MC74HC374ADWR2 SOIC–WIDE 1000 / Reel
MC74HC374ADT
TSSOP–20 75 / Rail
MC74HC374ADTR2 TSSOP–20 2500 / Reel
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 8
1
Publication Order Number:
MC74HC374A/D



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MC74HC374A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
V
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to VCC + 0.5
± 20
DC Output Current, per Pin
± 35
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
± 75
750
500
450
V
mA
mA
mA
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Plastic DIP, SOIC, SSOP or TSSOP Package)
– 65 to + 150
260
_C
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ*Maximum Ratings are those values beyond which damage to the device may occur.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
v vVout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
2.0
0
– 55
0
0
0
6.0
VCC
+ 125
1000
500
400
V
V
_C
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIH
Parameter
Minimum High–Level Input
Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIL MaximumLow–LevelInput
Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH
Minimum High–Level Output
Voltage
Test Conditions
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL |Iout|
v|Iout|
v|Iout|
2.4 mA
6.0 mA
7.8 mA
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
1.50 1.50 1.50
2.10 2.10 2.10
3.15 3.15 3.15
4.20 4.20 4.20
0.50 0.50 0.50
0.90 0.90 0.90
1.35 1.35 1.35
1.80 1.80 1.80
1.90 1.90 1.90
4.40 4.40 4.40
5.90 5.90 5.90
2.48 2.34 2.20
2.98 3.84 3.70
5.48 5.34 5.20
Unit
V
V
V
V
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MC74HC374A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
v v85_C
125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
Maximum Low–Level Output
Voltage
Maximum Input Leakage
Current
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL |Iout|
v|Iout|
v|Iout|
2.4 mA
6.0 mA
7.8 mA
Vin = VCC or GND
2.0
4.5
6.0
3.0
4.5
6.0
6.0
0.10
0.10
0.10
0.26
0.26
0.26
± 0.1
0.10
0.10
0.10
0.33
0.33
0.33
± 1.0
0.10
0.10
0.10
0.40
0.40
0.40
± 1.0
V
V
µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIOZ MaximumThree–State
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎLeakage Current
Output in High–Impedance State
6.0
± 0.5
± 5.0
± 10
µA
Vin = VIL or VIH
Vout = VCC or GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC Maximum Quiescent Supply Vin = VCC or GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCurrent (per Package)
Iout = 0 µA
6.0 4
40 160 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
VCC
V
– 55 to
25_C
v v85_C
125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎfmax
Maximum Clock Frequency (50% Duty Cycle)
2.0 6 5 4 MHz
3.0 15
10
8
4.5 30 24 20
6.0 35 28 24
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum Propagation Delay, Input Clock to Q
(Figures 1 and 5)
2.0 125 155 190 ns
3.0 80
110 130
4.5 25 31 38
6.0 21 26 32
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLZ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0 150 190 225 ns
3.0 100 125 150
4.5 30 38 45
6.0 26 33 38
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLZ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0 150 190 225 ns
3.0 100 125 150
4.5 30 38 45
6.0 26 33 38
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0 75
3.0 27
4.5 15
6.0 13
95 110 ns
32 36
19 22
16 19
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCout
Maximum Input Capacitance
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
10 10 10 pF
15 15 15 pF
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Enabled Output)*
34 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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MC74HC374A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSIMyttrmttsI,ÎÎÎÎwÎÎÎÎÎÎÎÎÎÎÎÎÎhNutbfGolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎREMMMMÎÎÎÎQÎÎÎÎÎÎÎÎÎÎÎÎÎiiiannnxUiiimmmimIÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎuuuRummmEmMPSHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInueoEpltlsudNueÎÎÎÎpÎÎÎÎÎÎÎÎÎÎÎÎÎtTTWRTiSmiiimsdÎÎÎÎeÎÎÎÎÎÎÎÎÎÎÎÎÎ(etCe,PhaC,L,anDlCÎÎÎÎrÎÎÎÎÎÎÎÎÎÎÎÎo=Îdaalco5mtFkac0aeÎÎÎÎtkÎÎÎÎÎÎÎÎÎÎÎÎÎtlopolteTFDCr,imaÎÎÎÎlÎÎÎÎÎÎÎÎÎÎÎÎIÎonteacpskuÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtÎtr =ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtf =ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ6.0 ÎÎÎÎÎÎÎÎnÎÎÎÎÎÎÎÎÎs) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎF3311igÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVV2346234623462346oC................l0050005000500050ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCtÎs ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖM5555541621195....i00003200000n5ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎto 2ÎÎÎÎÎÎÎÎÎÎÎÎ1ÎÎÎÎMÎ85450000_a0000Cx0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaÎÎÎÎÎÎÎÎÎÎÎÎMÎÎÎÎ5555Î65117211r...iv50315753a0000nnÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt8Îe5e_1Md854CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0ÎÎ000aL0000xi0mÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎit M555576119311ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎvÎ....Îi505302850000n12ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ51M_8540C000aÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0ÎÎ000x0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎUnnnnnssssÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎit
SWITCHING WAVEFORMS
CLOCK
Q
tr
90%
50%
tf
10%
tW
1/fmax
tPLH
90%
tPHL
50%
10%
tTLH tTHL
Figure 1.
VCC
GND
OUTPUT
ENABLE
Q
Q
50%
tPZL tPLZ
50%
tPZH tPHZ
50%
Figure 2.
VCC
GND
HIGH
IMPEDANCE
10% VOL
90% VOH
HIGH
IMPEDANCE
DATA
CLOCK
VALID
50%
tsu th
50%
Figure 3.
VCC
GND
VCC
GND
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