MC56F8157 Datasheet PDF - Motorola

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MC56F8157
Motorola

Part Number MC56F8157
Description (MC56F8157 / MC56F8357) 16-BIT HYBRID CONTROLLERS
Page 30 Pages


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56F8357/56F8157
Data Sheet
Preliminary Technical Data
56F8300
16-bit Hybrid Controllers
MC56F8357
Rev. 8.0
10/2004
freescale.com



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Document Revision History
Version History
Description of Change
Rev 1.0
Rev 2.0
Rev 3.0
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0
Rev 8.0
Initial Public Release
Added Package Pins to GPIO Table in Part 8 General Purpose Input/Output (GPIO). Added
“Typical Min” values to Table 10-17. Editing grammar, spelling, consistency of language throughout
family. Updated values in Regulator Parameters Table 10-9; External Clock Operation Timing
Requirements Table 10-13; SPI Timing Table 10-18; ADC Parameters Table 10-24; and IO Loading
Coefficients at 10MHz Table 10-25.
Corrected Table 4-6 Data Memory Map - changed address X:$FF0000 to X:$FFFF00
Added Part 4.8, added the word “access” to FM Error Interrupt in Table 4-5, documenting only Typ.
numbers for LVI in Table 10-6, updated EMI numbers and write-up in Part 10.8.
Updated numbers in Table 10-7 and Table 10-8 with more recent data. Corrected typo in Table 10-3
in Pd characteristics.
Replace any reference to Flash Interface Unit with Flash Module; removed references to JTAG pin
DE; corrected pin number for D14 in Table 2-2; added note to VCAP pin in Table 2-2; corrected
thermal numbers for 160 LQFP in Table 10-3; removed unneccessary notes in Table 10-12; corrected
temperature range in Table 10-14; added ADC calibration information to Table 10-24 and new graphs
in Figure 10-22.
Adding/clarifing notes to Table 4-4 to help clarify independent program flash blocks and other
Program Flash modes, clarification in Table 10-23, corrected Digital Input Current Low (pull-up
enabled) numbers in Table 10-5. Removed text and Table 10-2; replaced with note to Table 10-1.
Added 56F8157 information; edited to indicate differences in 56F8357 and 56F8157. Reformatted for
Freescale look and feel. Updated Temperature Sensor and ADC tables, then updated balance of elec-
trical tables for consistency throughout the family. Clarified I/O power description in Table 2-2, added
note to Table 10-7 and clarified Section 12.3.
Please see http://www.freescale.com for the most current Data Sheet revision.
56F8357 Technical Data, Rev. 8.0
2 Freescale Semiconductor
Preliminary



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56F8357/56F8157 General Description
Note: Features in italics are NOT available in the 56F8157 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 4MB of off-chip program and 32MB of
data memory
• Chip Select Logic for glueless interface to ROM and
SRAM
• 256KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 16KB of Data RAM
• 16KB Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
• Up to two Quadrature Decoders
• Optional on-chip regulator
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 76 GPIO lines
• 160-pin LQFP Package
RSTO EMI_MODE
RESET EXTBOOT
OCR_DIS
VPP VCAP VDD
VSS
VDDA VSSA
52
47
62
* Configuration
shown for on-chip
2.5V regulator
6 PWM Outputs
PWMA
3
Current Sense Inputs or GPIOC
4 Fault Inputs
6 PWM Outputs
PWMB
3
Current Sense Inputs or GPIOD
4 Fault Inputs
4 AD0
4
ADCA
AD1
Program Controller
and
Hardware Looping Unit
PAB
PDB
CDBR
CDBW
JTAG/
EOnCE
Port
Digital Reg
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
5 VREF
Memory
4 AD0 ADCB Program Memory
4 AD1
128K x 16 Flash
2K x 16 RAM
TEMP_SENSE
8K x 16
Quadrature
Boot Flash
4
Decoder 0 or
Quad
Data Memory
4K x 16 Flash
Timer or /
8K x 16 RAM
GPIOC
Quadrature
Decoder 1 or
4 Quad
Timer B or
SPI1 or GPIOC
2
Quad
Timer C or
Decoding
GPIOE Peripherals
Quad
4 Timer D or
GPIOE
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW IPAB
Control
IPWDB IPRDB
Clock
resets
External
Address Bus
Switch
6
2
8
4
1
3
External Data 7
Bus Switch 9
Bus Control 6
PLL
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0-3 (A16-19)
GPIOB4 (A20,
prescaler_clock)
GPIOB5-7 (A21-23,
clk0-3**)
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
GPIOD0-5 or CS2-7
PS (CS0) or GPIOD8
DS (CS1) or GPIOD9
**See Table 2-2
for explanation
2
FlexCAN
SPI0 or SCI1 or SCI0 or COP/
GPIOE GPIOD GPIOE Watchdog
Interrupt
Controller
System P
Integration
O
R
Module
Clock O
Generator
S
C
XTAL
EXTAL
4 22
IRQA IRQB
CLKO CLKMODE
56F8357/56F8157 Block Diagram
Freescale Semiconductor
Preliminary
56F8357 Technical Data, Rev. 8.0
3



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Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
1.1. 56F8357/56F8157 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . 9
1.4. Architecture Block Diagram . . . . . . . . . . . . 10
1.5. Product Documentation . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions . . . . . . . . . . . . . . 14
Part 2: Signal/Connection Descriptions . . . 15
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
Part 3: On-Chip Clock Synthesis (OCCS) . . 38
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2. External Clock Operation . . . . . . . . . . . . . . 38
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 40
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . 41
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 43
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 46
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 48
4.7. Peripheral Memory Mapped Registers . . . . 49
4.8. Factory Programmed Memory . . . . . . . . . . 75
Part 5: Interrupt Controller (ITCN) . . . . . . . . 76
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3. Functional Description . . . . . . . . . . . . . . . . 76
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 78
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 78
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 79
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Part 6: System Integration Module (SIM) . 106
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . 107
6.4. Operation Mode Register . . . . . . . . . . . . . 108
6.5. Register Descriptions . . . . . . . . . . . . . . . . 108
6.6. Clock Generation Overview . . . . . . . . . . . 121
6.7. Power Down Modes Overview . . . . . . . . . 122
6.8. Stop and Wait Mode Disable Function . . . 122
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Part 7: Security Features . . . . . . . . . . . . . . 123
7.1. Operation with Security Enabled . . . . . . . 123
7.2. Flash Access Blocking Mechanisms . . . . 124
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . 126
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 126
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 127
8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . 127
Part 9: Joint Test Action Group (JTAG) . 132
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . .132
Part 10: Specifications . . . . . . . . . . . . . . . 132
10.1. General Characteristics . . . . . . . . . . . . . .132
10.2. DC Electrical Characteristics . . . . . . . . . . 136
10.3. AC Electrical Characteristics . . . . . . . . . . 140
10.4. Flash Memory Characteristics . . . . . . . . . 140
10.5. External Clock Operation Timing . . . . . . . 141
10.6. Phase Locked Loop Timing . . . . . . . . . . .141
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 142
10.8. External Memory Interface Timing . . . . . .142
10.9. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . 145
10.10. Serial Peripheral Interface (SPI) Timing . 147
10.11. Quad Timer Timing . . . . . . . . . . . . . . . . 151
10.12. Quadrature Decoder Timing . . . . . . . . . . 151
10.13. Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . . 152
10.14. Controller Area Network (CAN) Timing . 153
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 153
10.16. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . . 155
10.17. Equivalent Circuit for ADC Inputs . . . . . .158
10.18. Power Consumption . . . . . . . . . . . . . . . . 158
Part 11: Packaging . . . . . . . . . . . . . . . . . . 160
11.1. 56F8357 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 160
11.2. 56F8157 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 163
Part 12: Design Considerations . . . . . . . . 167
12.1. Thermal Design Considerations . . . . . . . . 167
12.2. Electrical Design Considerations . . . . . . . 168
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . .169
Part 13: Ordering Information . . . . . . . . . 170
56F8357 Technical Data, Rev. 8.0
4 Freescale Semiconductor
Preliminary



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